Foundations — Fan-in and fan-out limits

Before you can read the parent note, you must own every symbol it throws at you. This page builds each one from nothing — plain words, a picture, and why the topic needs it — in an order where each idea leans on the one before. Start at line one; assume you have seen none of the notation.

0. The two words themselves

Look at the figure: the red box is our gate. Three black arrows enter (fan-in = 3). Four black arrows leave, each going to a different downstream box (fan-out = 4). That is the entire vocabulary — the rest of this page explains why each of those arrows costs time.

1. Voltage, the "height of water" — $V$ and $V_{DD}$

Digital logic only cares about two heights: full and empty.

Why the topic needs it: the parent note writes $V(t)=V_{DD}(1-e^{-t/RC})$ — the output climbing from empty toward the full rail. You cannot read that line without knowing $V_{DD}$ is the ceiling.

2. Capacitance $C$ — a bucket that stores charge

Every gate input behaves like a small bucket, because it is a transistor gate terminal — a tiny insulated plate that stores charge.

In the figure, the red output wire fills four black buckets ($4C_g$) plus its own small parasitic bucket $C_{par}$. That is exactly the parent's Step 1: $C_L=h{C}_g+C_{par}$ where $h$ is just the count of buckets (the fan-out).

3. Current $I$ and Resistance $R$ — flow and the narrow pipe

The link between all three is Ohm's law, the one rule you must trust:

A switched-on transistor is not a perfect wire — it behaves like a fixed resistor $R$. That single fact is why filling a bucket takes time instead of happening instantly.

This is the parent's mnemonic made concrete: IN series, OUT parallel. Fan-in stacks resistors (series), fan-out stacks capacitors (parallel). Build these two pictures now and the rest of the topic is bookkeeping. See RC Delay Model and Transistor Sizing.

4. The RC time constant — why filling takes time

Now combine a resistor $R$ (the transistor) feeding a capacitor $C$ (the load). Open the tap and the bucket does not fill instantly: the fuller it gets, the smaller the pressure difference driving more water in, so it slows as it approaches full. This gives the classic charging curve.

The exact climb is the parent's equation: $V(t)=V_{DD}\left(1-e^{-t/RC}\right)$

Here $e$ is a fixed number ($\approx 2.718$) that shows up whenever something grows or decays proportional to how far it still has to go — exactly our "fills slower as it gets fuller" situation. You do not need to derive $e$; you need to know it is the fingerprint of this smooth-slowing fill.

5. From volts to normalized delay — $g$, $f$, $p$, $d$, $\tau$

Real numbers like "$R=8\text{ k}\Omega$, $C=3\text{ fF}$" are clumsy. Engineers strip out the messy units by measuring delay in multiples of a reference — the delay of one plain inverter. This is the logical-effort language (see Logical Effort).

6. Transistors, NMOS/PMOS, and why NOR is poorer

7. Putting the symbols in order

Read top to bottom: voltage/current/resistance give Ohm's law; Ohm's law plus capacitance gives the RC clock; the RC clock gives real delay; normalizing gives $d=gf+p$; series stacking (fan-in) and parallel loading (fan-out) both feed that equation — and that is the topic.

Equipment checklist

Cover the right side. If you can answer each, you are ready for the parent note and for inverter chains and timing.

Connections

• Fan-in and fan-out limits — the parent note these foundations feed into.
• RC Delay Model — the $0.69RC$ built here in full.
• Logical Effort — the $d=gf+p$ framework whose symbols we defined.
• CMOS Static Logic Gates — how the NMOS/PMOS networks are wired.
• Transistor Sizing — widening pipes to fight $R_{stack}$.
• Buffer Sizing and Inverter Chains — the fan-out fix.
• Propagation Delay and Timing — where delay becomes clock speed.