Fan-in and fan-out limits: Worked examples — Hardware deep dive

Before we start, one promise: every symbol used here is defined first. Let me re-anchor the numbers we lean on hardest, in plain words.

Definition The four numbers in

$d = g f + p$

$g$ = logical effort. Read it as: "how many times harder is this gate to switch than a plain inverter of the same drive?" An inverter has $g = 1$ by definition. A NAND-2 has $g = \frac{4}{3}$ , meaning it is $\frac{4}{3} \times$ worse.
$f$ = electrical effort = fan-out = $\frac{C _{o u t}}{C _{in}}$ , using the two capacitances just defined. Read it as: "how much bigger is the capacitance I must drive than the capacitance I present?" If I drive 4 copies of myself, $f = 4$ .
$p$ = parasitic delay. The delay a gate has even driving nothing, from its own internal source/drain junction capacitance. An inverter has $p = 1$ (in units of $p_{inv}$ ).
$d$ = total delay in $τ$ units (one $τ$ = the delay of an ideal inverter driving one identical inverter with no parasitics). This $d$ is the dimensionless, normalised form of the physical delay $t_{p d}$ (measured in real seconds) that we meet in Example 8: $t_{p d} = d \cdot τ$ .

Formula Where the parasitic delay

$p = N$ comes from (built here, not assumed) Picture an $N$ -input NAND: $N$ NMOS transistors stacked in series. Between every pair of stacked transistors sits one internal node — a source/drain junction — and each such junction is a little capacitor the gate must charge before the output moves. One inverter has essentially one such drain junction on its output, giving parasitic delay $p_{inv} = 1$ .

Stacking $N$ transistors gives roughly $N$ junction caps of the same size, so $p_{NAND- N} \approx N p_{inv} = N .$
A NOR- $N$ stacks $N$ PMOS in series and has the same count of internal junctions, so its parasitic delay is also $p_{NOR- N} \approx N$ (the PMOS penalty shows up in $g$ , not $p$ ). This is why every fan-in example below writes $p = N$ : it is the number of stacked junctions, each worth one $p_{inv}$ .

Everything below is arithmetic on these numbers. The framework is Logical Effort; the $0.69 R C$ underneath it is RC Delay Model.

The scenario matrix

Here is the full grid of case-classes this topic can throw at you. Each of the ten examples is tagged with the cell(s) it covers.

Case class	What makes it special	Covered by
Inverter, normal fan-out	baseline $g = 1$	Ex 1
Fan-out = 0 (degenerate)	drives nothing, $f = 0$	Ex 2
Fan-out very large (limiting)	$f \to$ big, delay $\to$ linear ramp	Ex 3
NAND- $N$ fan-in sweep	$g, p$ both grow with $N$	Ex 4
NOR vs NAND (sign of "which is worse")	PMOS stack, factor of 2	Ex 5
Split big gate → tree (design fix)	fan-in trade	Ex 6
Fan-out fix by buffering	insert inverters	Ex 7
Real-world word problem	real ns / ps numbers	Ex 8
Current-limited fan-out (TTL edge case)	$I_{O H} / I_{in}$ , not capacitance	Ex 9
Exam twist: minimum delay of a chain	optimal stage effort $f = N F$	Ex 10

The two axes that generate "every case" are: which network the fan-in stresses (NMOS pull-down for NAND, PMOS pull-up for NOR) and how large the fan-out is (zero → one → many → optimal). We hit every corner.

Worked Examples

The figure plots $d = 1 \cdot f + 1$ as a straight line. Example 1 is the pale-yellow dot at $f = 3$ . Notice the line is straight — that is the whole "delay grows linearly with fan-out" claim, drawn.

Worked example Example 2 — Fan-out = 0 (degenerate cell)

The same inverter drives nothing (output left floating, e.g. it is the last stage feeding a scope probe of negligible cap). What is $d$ ?

Forecast: is the delay zero? Careful.

Set $f = 0$ . No load capacitance beyond the gate's own internals, so $C_{o u t} = 0 \Rightarrow f = 0$ . Why this step? We must check the boundary; formulas are only trustworthy if they behave sanely at the edges.
Plug in. $d = 1 \cdot 0 + 1 = 1$ . Why this step? The $g f$ term vanishes but $p$ does not — the gate still has to charge its own drain junctions.

Answer: $1 τ$ , not $0$ .

Verify: this is exactly the meaning of parasitic delay $p$ : the intrinsic delay when driving zero external load. A gate is never instantaneous. ✓ Look at the blue dot at $f = 0$ on the figure — the line crosses the vertical axis at $d = p = 1$ , never at 0.

Worked example Example 3 — Fan-out very large (limiting cell)

The inverter now drives 20 loads. Find $d$ , and describe the behaviour as $f \to \infty$ .

Forecast: roughly 20? more? less?

$f = 20$ . Twenty equal loads. Why this step? Same load-counting rule as Ex 1; we push it to a big value to see the trend.
$d = 1 \cdot 20 + 1 = 21$ . Why this step? Direct substitution into $d = g f + p$ .
Limiting behaviour. As $f \to \infty$ , $d \approx g f = f$ : the constant $p$ becomes negligible and delay is directly proportional to fan-out. Why this step? This tells us a huge fan-out is linearly punishing — and warns us (Ex 7) that a single stage should never eat a giant $f$ ; we split it with buffers so each stage sees a modest effort.

Answer: $21 τ$ ; asymptotically $d \to f$ .

Verify: slope of the line is $g = 1$ , intercept $p = 1$ ; at $f = 20$ , $d = 21$ sits right on the extended line in the figure. Doubling to $f = 40$ would give $d = 41$ — nearly double, confirming linear growth. ✓

Worked example Example 4 — NAND-

$N$ fan-in sweep (fan-in cell, NMOS stack) For a fixed fan-out $f = 4$ , compute delay of NAND-2, NAND-3, NAND-4. Use $g = \frac{N + 2}{3}$ , $p = N$ (in $p_{inv}$ units, as built above).

Forecast: will delay grow slowly (linear in $N$ ) or fast?

NAND-2: $g = \frac{4}{3}$ , $p = 2$ . $d = \frac{4}{3} \cdot 4 + 2 = \frac{16}{3} + 2 = \frac{22}{3} \approx 7.33$ . Why this step? Apply the NAND logical-effort formula at $N = 2$ and its two-junction parasitic $p = 2$ , then substitute into $d = g f + p$ .
NAND-3: $g = \frac{5}{3}$ , $p = 3$ . $d = \frac{5}{3} \cdot 4 + 3 = \frac{20}{3} + 3 = \frac{29}{3} \approx 9.67$ . Why this step? Same substitution at $N = 3$ ; note $g$ rose from $\frac{4}{3}$ to $\frac{5}{3}$ and $p$ rose from 2 to 3 — both terms climb together.
NAND-4: $g = 2$ , $p = 4$ . $d = 2 \cdot 4 + 4 = 12$ . Why this step? Same recipe at $N = 4$ ; each added input raises both $g$ (steeper line) and $p$ (higher intercept), so the same fan-out $f = 4$ costs more each time — that is the super-linear fan-in penalty.

Answers: $7.33 τ, 9.67 τ, 12 τ$ .

Verify: differences are $9.67 - 7.33 = 2.33$ and $12 - 9.67 = 2.33$ ... equal here because at fixed $f = 4$ each step adds $Δ g \cdot 4 + Δ p = \frac{1}{3} \cdot 4 + 1 = \frac{7}{3} \approx 2.33$ — a constant per-input hit at this $f$ , but note it grows with $f$ . ✓

The bars show NAND-2/3/4 climbing. See Transistor Sizing for why you can't just widen the stack away — wider transistors raise the previous stage's fan-out.

Worked example Example 5 — NOR vs NAND, "which is worse" (sign-of-comparison cell, PMOS stack)

Compare a NOR-3 with a NAND-3 at fan-out $f = 4$ . Use $g_{NOR} = \frac{2 N + 1}{3}$ , $g_{NAND} = \frac{N + 2}{3}$ , $p = N$ for both.

Forecast: how much worse is NOR? A little, or roughly 2× on the effort term?

NAND-3: $g = \frac{5}{3}$ , $p = 3$ , $d = \frac{5}{3} \cdot 4 + 3 = \frac{29}{3} \approx 9.67$ . Why this step? We need the NAND baseline to compare against; it is the same NAND-3 substitution as in Ex 4, restated here so the comparison stands on its own.
NOR-3: $g = \frac{2 \cdot 3 + 1}{3} = \frac{7}{3}$ , $p = 3$ , $d = \frac{7}{3} \cdot 4 + 3 = \frac{28}{3} + 3 = \frac{37}{3} \approx 12.33$ . Why this step? NOR stacks PMOS in series. PMOS carries ~half the current per width (mobility ~2× lower), so to match drive you widen it more → larger $g$ . The " $2 N$ " in the formula is that mobility penalty made numeric.
Compare the effort terms. $g_{NOR} f = \frac{28}{3} \approx 9.33$ vs $g_{NAND} f = \frac{20}{3} \approx 6.67$ . Ratio $= \frac{28}{20} = 1.4$ . Why this step? Isolating the $g f$ term removes the shared $p = 3$ so we see purely how much the logical effort (the PMOS penalty) costs.

Answer: NOR-3 $\approx 12.33 τ$ vs NAND-3 $\approx 9.67 τ$ — NOR is $\approx 27%$ slower here.

Verify: as $N \to \infty$ , $\frac{g _{NOR}}{g _{NAND}} = \frac{2 N + 1}{N + 2} \to 2$ , confirming NOR's effort grows toward twice NAND's — the "NOR is poorer" mnemonic, proven. ✓

Worked example Example 6 — Split a big gate into a tree (design-fix cell)

You need an 8-input AND. Option A: one NAND-8 (single monolithic gate). Option B: a tree built from NAND-2 gates. Compare the worst single-gate delay (the largest $g f + p$ of any one gate in the design), both at fan-out $f = 4$ .

Forecast: how much does the monster NAND-8 gate cost vs one NAND-2 gate?

NAND-8 (Option A worst gate): $g = \frac{8 + 2}{3} = \frac{10}{3}$ , $p = 8$ . $d = \frac{10}{3} \cdot 4 + 8 = \frac{40}{3} + 8 = \frac{64}{3} \approx 21.33$ . Why this step? One giant gate concentrates all the series penalty into a single stage — huge $g$ and huge $p$ . This one gate is the whole delay.
NAND-2 (Option B worst gate): $g = \frac{4}{3}$ , $p = 2$ , $d = \frac{4}{3} \cdot 4 + 2 = \frac{22}{3} \approx 7.33$ . Why this step? In the tree, no single gate ever has fan-in above 2, so the worst gate is only a NAND-2 — nearly 3× smaller per-gate delay.

Answer (metric = worst single-gate delay): the monolithic NAND-8 gate is $\frac{64}{3} \approx 21.33 τ$ ; the worst gate in the NAND-2 tree is only $\frac{22}{3} \approx 7.33 τ$ .

Caveat on the metric: the total path delay of a tree sums its depth (~3 NAND-2 stages, roughly $3 \times 7.33 \approx 22 τ$ ), so a naive tree is not automatically faster than the monolith end-to-end. The real win is that each tree gate is small, so it can be independently sized and its fan-out spread — an optimized tree (per Ex 10's equal-effort rule) beats the monolith, and the tree also removes the crippling series- $R$ /single-node bottleneck of an 8-stack.

Verify: $\frac{64/3}{22/3} = \frac{64}{22} \approx 2.9$ — the NAND-8 gate is nearly 3× a NAND-2 gate on the per-gate metric we defined. ✓

Worked example Example 7 — Fix a big fan-out with a buffer (fan-out-fix cell)

A gate must drive $f = 64$ (a wide bus). Instead of one stage eating $f = 64$ , insert a chain. What per-stage effort minimizes delay, and how many stages? (Preview of Buffer Sizing and Inverter Chains.)

Forecast: should each inverter grow by 2×? 4×? and how many?

Total effort $F = 64$ (assume $g = 1$ inverters so path effort = electrical effort). Why this step? We must spread $F$ across $n$ stages so no stage is overloaded.
Optimal per-stage effort. Minimum delay occurs when each stage has equal effort $f = n F$ . The classic near-optimum is $f \approx 4$ (ideally $e \approx 2.7$ , ~4 once parasitics count). Why this step? Delay of a chain is $n F^{1/ n}$ ; minimizing over $n$ gives $F^{1/ n} = e$ . This is the exam-favourite result.
Number of stages for $f = 4$ : $n = lo g_{4} 64 = 3$ . Why this step? $4^{3} = 64$ . Three inverters, each 4× the previous.
Chain delay: $d = n \cdot f = 3 \cdot 4 = 12 τ$ (ignoring $p$ ). Why this step? Compare to driving $f = 64$ in one stage: $d = 1 \cdot 64 = 64 τ$ . Buffering wins massively.

Answer: 3 stages, per-stage $f = 4$ , chain delay $\approx 12 τ$ vs $64 τ$ unbuffered.

Verify: $4^{3} = 64$ ✓; $3 \times 4 = 12 < 64$ ✓. Fan-out effects "ripple backward": each inserted buffer presents small input cap to the stage before it, exactly the parent's point. ✓

Worked example Example 8 — Real-world word problem (real-time units cell)

A driver has on-resistance $R = 2 k Ω$ . Each load gate is $C_{g} = 2 fF$ . The driver's own parasitic cap is $C_{p a r} = 3 fF$ . It drives $h = 5$ loads, where $h$ is simply the fan-out counted as a whole number of gates (the integer version of $f$ ). Find the propagation delay $t_{p d}$ — the physical delay in real seconds, using $t_{p d} = 0.69 R C_{L}$ .

Forecast: tens of ps? hundreds?

Total load. $C_{L} = h C_{g} + C_{p a r} = 5 \cdot 2 + 3 = 13 fF$ . Why this step? Loads add in parallel (fan-out is capacitance-in-parallel), plus the driver's self-cap. Here $C_{L}$ is just $C_{o u t}$ written with real numbers.
Why $t_{p d}$ and not $d$ ? $d$ was our dimensionless delay in $τ$ -units; here we want an actual time in seconds, so we use the physical form $t_{p d} = 0.69 R C_{L}$ (they are the same delay, different units: $t_{p d} = d \cdot τ$ ). Why this step? The exam asks for picoseconds, not $τ$ , so we must return to the RC form where $R$ and $C$ carry real units.
RC delay. $t_{p d} = 0.69 \cdot R \cdot C_{L} = 0.69 \cdot (2000 Ω) \cdot (13 \times 1 0^{- 15} F)$ . The $0.69$ is the 50%-crossing factor from $V = V_{D D} (1 - e^{- t / R C})$ — see RC Delay Model.
Compute. $2000 \cdot 13 \times 1 0^{- 15} = 2.6 \times 1 0^{- 11} s = 26 ps$ ; times $0.69$ gives $t_{p d} = 17.94 ps$ .

Answer: $t_{p d} \approx 17.94 ps$ (about $18 ps$ ).

Verify (units): $Ω \cdot F = s$ , so $2 k Ω \cdot 13 fF = 26 ps$ before the 0.69 factor. Sanity: dropping to $h = 1$ load gives $C_{L} = 5 fF$ , $t_{p d} = 0.69 \cdot 2000 \cdot 5 \times 1 0^{- 15} = 6.9 ps$ — smaller fan-out, smaller delay, as required. ✓ Links to Propagation Delay and Timing.

Worked example Example 9 — Current-limited fan-out (TTL-interface edge case)

A CMOS gate driving a legacy TTL bus can source $I_{O H} = 4 mA$ at the high level. Each TTL input sinks $I_{in} = 40 μ A$ . What is the static fan-out limit? Contrast with pure CMOS.

Forecast: is the limit huge (thousands) or modest?

Divide the currents. Max loads $= ⌊ \frac{I _{O H}}{I _{in}} ⌋ = ⌊ \frac{4 \times 1 0 ^{- 3}}{40 \times 1 0 ^{- 6}} ⌋ = ⌊ 100 ⌋ = 100$ . Why this step? The output current splits among the loads; too many and the high level sags below $V_{I H}$ , corrupting logic. This is a DC current limit, unlike the AC/capacitive limit everywhere else on this page.
Pure-CMOS contrast. A CMOS gate input draws $I_{in} \approx 0$ (gate leakage), so this current limit $\to \infty$ . There the binding limit is speed (capacitance), i.e. $d = g f + p$ , not current. Why this step? Cover both regimes so no exam case surprises you.

Answer: static fan-out limit $= 100$ for the TTL interface; effectively unlimited (speed-bound) in pure CMOS.

Verify: $100 \cdot 40 μ A = 4 mA = I_{O H}$ exactly — the 101st load would exceed the source current. ✓

Worked example Example 10 — Exam twist: minimum delay of a full path (optimal-effort cell)

A path of $n = 3$ gates has total logical effort $G = 2$ and total electrical effort $H = 4$ . Find the minimum path delay (parasitics ignored).

Forecast: is min delay simply $G \cdot H$ ? Or a root of it?

First, the two new symbols, defined before use:

$G$ = path logical effort = the product of the individual $g$ 's of every gate on the path, $G = g_{1} g_{2} \dots g_{n}$ . Here $G = 2$ .
$H$ = path electrical effort = the overall $\frac{C _{final load}}{C _{first input}}$ of the whole path. Here $H = 4$ .
$F$ = path effort = $G \cdot H$ = the total "work" the path must do. It is the multi-stage generalisation of the single-stage $f$ .

Compute the path effort. $F = G \cdot H = 2 \cdot 4 = 8$ . Why this step? Just as one stage's work is its $f$ , the whole path's work is the product $G \cdot H$ ; this single number sets the achievable speed.
Best per-stage effort. $\hat{f} = F^{1/ n} = 8^{1/3} = 2$ . Why this step? Path delay is minimized when every stage carries the same stage effort $\hat{f} = F^{1/ n}$ ; unequal efforts always cost more (a consequence of the AM–GM inequality — the sum is smallest when the terms are equal).
Minimum delay. $D_{m i n} = n \cdot \hat{f} = 3 \cdot 2 = 6 τ$ (parasitics ignored). The general formula is $D_{m i n} = n F^{1/ n}$ . Why this step? Add up $n$ equal stage efforts of $\hat{f}$ each.

Answer: $\hat{f} = 2$ per stage, $D_{m i n} = 6 τ$ .

Verify: $2^{3} = 8 = F$ ✓; any uneven split, e.g. stage efforts $1, 2, 4$ (still multiplying to $8$ ), gives $1 + 2 + 4 = 7 > 6$ ✓ — equal effort wins, confirming the AM–GM minimum. Framework: Logical Effort. ✓

Recall Rapid re-derivation checklist

Given a gate: (1) find $g$ from its family formula, (2) find $f = C_{o u t} / C_{in}$ , (3) find $p \approx N p_{in v}$ (one per stacked junction), (4) $d = g f + p$ . For a chain, compute $F = G \cdot H$ and spread it so each stage sees $\hat{f} = F^{1/ n} \approx 4$ . For a big fan-in, split into a tree. For a big fan-out, add buffers.

Fan-out = 0 ⇒ delay equals what?

The parasitic delay

p

(never zero).

Where does

p = N

for a NAND-

N

come from?

Roughly one internal source/drain junction cap per stacked transistor, each worth

p_{inv}

, so

p \approx N p_{inv}

NAND-4 at

f = 4

delay?

12 τ

(

g = 2, p = 4

NOR-3 vs NAND-3 at

f = 4

12.33 τ

9.67 τ

; NOR is worse (PMOS stack).

Difference between

d

and

t_{p d}

d

is dimensionless delay in

τ

-units;

t_{p d}

is the same delay in real seconds,

t_{p d} = d \cdot τ = 0.69 R C_{L}

Path effort

F

defined?

F = G \cdot H

, product of path logical effort and path electrical effort.

Minimum path delay of

n

stages?

D_{m i n} = n F^{1/ n}

, achieved with equal per-stage effort

\hat{f} = F^{1/ n}

Current-limited fan-out formula?

⌊ I_{O H} / I_{in} ⌋

Connections

Logical Effort — the $d = g f + p$ and $D = n F^{1/ n}$ engine used in every example.
RC Delay Model — the $0.69 R C$ behind Example 8.
Buffer Sizing and Inverter Chains — Examples 7 and 10.
Transistor Sizing — why widening the stack (Ex 4) shifts cost backward.
Propagation Delay and Timing — turning $τ$ into ns.
CMOS Static Logic Gates — the NAND/NOR networks whose stacks set fan-in.

Worked examples — Fan-in and fan-out limits

The scenario matrix

Worked Examples

Connections

Case Map