Fan-in and fan-out limits: Question bank — Hardware deep dive

Before any trap can bite, every symbol on this page must mean something to you. Let us earn each one against a picture.

Definition The five symbols this page uses

$R$ = the on-resistance of one turned-on transistor — when a transistor is "on" it is not a perfect wire; it behaves like a small resistor of value $R$ that current must fight through to charge or drain the output. Picture it as a narrow pipe: the "on" transistor is a pipe of a fixed narrowness.
$C_{g}$ = the input capacitance of one gate input (one load) — every input you drive is really a tiny capacitor to ground, $C_{g}$ , that must be filled with charge before its voltage moves.
$h$ = the number of identical loads the output drives. Fan-out counts them.
$C_{p a r}$ = the driver's own parasitic (self) capacitance — charge stuck on the gate's own internal junctions, present even with nothing attached.
$C_{in}$ , $C_{o u t}$ = the gate's own input capacitance and its total output load capacitance.

See the pictures below before reading on.

Now the delay law. A gate charges its load $C_{L}$ through its on-resistance $R$ — an RC circuit — so its delay is proportional to $R C_{L}$ (this is the $0.69 R C$ story from RC Delay Model). To compare gate types fairly we split that product into three named pieces, benchmarked against an inverter.

Intuition Where the

$+ 2$ and $+ 1$ in the logical-effort formulas come from Study figure s02. To make a NAND- $N$ pull down as strongly as an inverter, its $N$ series NMOS must each be widened by $N$ (to cancel the $N R$ stack), while its $N$ parallel PMOS stay at inverter width. Add up the input capacitance one input drives: it touches one NMOS of width $N$ and one PMOS of width 2 (PMOS is ~2× wide for equal drive). So per input the capacitance is $N + 2$ , versus an inverter's reference of $3$ (a width-1 NMOS + width-2 PMOS): $g_{N A N D} = \frac{N + 2}{3}$ For a NOR- $N$ the roles swap: the PMOS are now the series stack and must each be widened by $2 N$ (they start at 2 and stack $N$ deep), while the NMOS stay at width 1. One input touches a PMOS of width $2 N$ + an NMOS of width $1$ : $g_{N O R} = \frac{2 N + 1}{3}$ The " $+ 2$ " is the untouched PMOS pair in a NAND; the " $+ 1$ " is the untouched NMOS in a NOR. The bigger leading term ( $2 N$ vs $N$ ) is why NOR grows twice as fast.

Now you own every symbol. On to the traps — cover the answer, reason aloud, then reveal.

True or false — justify

Doubling the fan-out of a gate roughly doubles its effort delay

g f

True.

f = C_{o u t} / C_{in}

is linear in the load, and

d = g f + p

is linear in

f

, so the

g f

term doubles (the fixed

p

does not, so total delay a little less than doubles).

A NAND-4 and a NOR-4 have the same logical effort.

False.

g_{N A N D} = (N + 2) /3 = 2

but

g_{N O R} = (2 N + 1) /3 = 3

. NOR stacks weak PMOS in series, so its effort grows about twice as fast with

N

Fan-out only slows down the gate that is driving the load.

False. Fixing high fan-out usually means upsizing the driver, which raises its input capacitance and slows the stage before it — the penalty ripples backward, which is exactly why buffer chains exist.

In pure static CMOS, the practical fan-out limit is set by DC output current.

False. CMOS gate leakage

I_{in} \approx 0

, so almost no static current is drawn. The limit is capacitance (speed); the current limit only dominates in TTL or off-chip interfaces.

The "0.69" in

t_{p d} = 0.69 R C

is an empirical fudge factor with no derivation.

False. It is

ln 2

. Solving

V (t) = V_{D D} (1 - e^{- t / R C})

for the 50% crossing gives

t = R C ln 2 \approx 0.69 R C

— pure algebra, see RC Delay Model.

Widening every transistor in a NAND stack by

N

makes the gate strictly faster.

False. It restores the drive resistance to a single-transistor value, but each wider transistor now presents

N \times

the input capacitance, loading the previous stage. You trade fan-in resistance for upstream fan-out — a wash unless you rebalance the whole chain.

Parasitic delay

p

depends on how much load the gate drives.

False.

p

comes from the gate's own internal junction/self capacitance

C_{p a r}

and is present even at zero external load. Only the

g f

term scales with the load

f

A single 8-input NAND is smaller and therefore faster than a tree of 2-input NANDs doing the same logic.

False (on speed). Fewer transistors ≠ faster. The 8-stack has

R_{s t a c k} = 8 R

and

p \approx 8 p_{in v}

; delay grows super-linearly with fan-in, so a balanced tree of low-fan-in gates wins despite more gates.

For a NAND gate, fan-in stresses the PMOS pull-up network.

False. A NAND has its inputs in series in the NMOS pull-down; the PMOS are in parallel. It is the NOR that puts PMOS in series, which is why NOR suffers more.

Spot the error

"Fan-in is the number of gates connected to a gate's output."

Wrong — that's fan-out. Fan-in is the number of inputs the gate accepts (equivalently, transistors in series in one network).

"Because resistors in series add, stacking

N

NMOS gives

R_{s t a c k} = R / N

The formula is inverted. Series on-resistances add, so

R_{s t a c k} = N R

. Dividing (

R / N

) is what parallel resistances do — that would describe the parallel pull-up of a NAND, not the series pull-down.

"Loads add in series, so total load capacitance is

C_{L} = C_{g} / h

for

h

loads."

Wrong on both counts. Each driven input is a capacitor

C_{g}

to ground;

h

of them sit in parallel, and parallel capacitances add:

C_{L} = h C_{g} + C_{p a r}

"Electrical effort is

f = C_{in} / C_{o u t}

Inverted.

f = C_{o u t} / C_{in}

— output (load) over the gate's own input capacitance. A big load with a small driver gives a large

f

(hard job), which the ratio must reflect as

> 1

"Since NOR and NAND are logic-duals, in CMOS we should prefer NOR for high fan-in."

Backwards. NOR's series PMOS (low mobility) makes

g_{N O R} = (2 N + 1) /3

grow twice as fast. In CMOS you prefer NAND logic — "NOR is poorer."

"Parasitic delay of a NAND-

N

stays at

p_{in v}

regardless of

N

Wrong. Each internal source/drain junction between stacked transistors adds capacitance, so

p_{N A N D - N} \approx N p_{in v}

— it grows with fan-in.

"To speed up a net driving 30 loads, just make the driver enormous — one giant transistor solves it."

Only half-right. A giant driver charges the 30 loads fast but presents a huge input capacitance to its predecessor, which then becomes the bottleneck. The correct fix is a staged buffer/inverter chain that spreads the effort geometrically.

Why questions

Why does delay grow linearly with fan-out but super-linearly with fan-in?

Fan-out adds capacitance linearly (

C_{L} = h C_{g}

) into a linear RC law. Fan-in raises both

g

(through the

+ 2

+ 1

numerator terms) and

p

(

\approx N p_{in v}

) simultaneously, so their product compounds faster than linearly.

Why does the RC time constant even appear — why not just a fixed switching time?

A CMOS output charges a capacitor

C_{L}

through a transistor of on-resistance

R

; that RC circuit relaxes exponentially, so the 50% crossing time is

\propto R C

, not a constant. See RC Delay Model.

Why does raising fan-in force the previous stage to work harder?

To keep

R_{s t a c k} = N R

from slowing the gate, you widen the stacked transistors by

N

, which multiplies their input capacitance — that extra cap becomes the previous stage's load (fan-out). The cost migrates upstream. See Transistor Sizing.

Why is logical effort

g

measured relative to an inverter?

An inverter is the simplest drive-a-cap-through-one-transistor reference (

g = 1

g

then answers "how many times worse is this gate than an inverter at delivering the same drive?", making gate types directly comparable in the

d = g f + p

framework of Logical Effort.

Why does the "2" appear in

g_{N O R} = (2 N + 1) /3

but not in

g_{N A N D}

PMOS carriers (holes) have roughly half the mobility of NMOS electrons, so a PMOS must be ~2× wider for equal drive. NOR stacks these wide PMOS in series, doubling the input-capacitance cost per input.

Why can splitting a big gate into a tree of small gates reduce total delay even though it adds gates and levels of logic?

Each small gate has low

g

and low

p

, and the load per stage stays modest, so per-stage delay is small. The super-linear penalty of one huge fan-in gate outweighs the extra (but shallow, additive) delay of a balanced tree.

Edge cases

What is the fan-out of a gate whose output drives nothing (an open output)?

Strictly

f = C_{o u t} / C_{in}

with

C_{o u t} = C_{p a r}

only, so

f = C_{p a r} / C_{in}

— small but not identically zero. Delay approaches the parasitic floor

d \approx p

; the gate can never be faster than its own

p

For a fan-in of

N = 1

, what does a NAND/NOR become and how do

g

and

p

change?

A single input/single-transistor network is just an inverter:

g_{N A N D} = (1 + 2) /3 = 1

and

g_{N O R} = (2 \cdot 1 + 1) /3 = 1

, both collapsing to the inverter's

g = 1

. The parasitic also drops from the two-transistor-stack value (

p \approx N p_{in v}

) down to

p \approx p_{in v}

, since there are no internal series junctions left.

Is there a maximum useful fan-out per stage, or can one strong gate drive unlimited loads?

There is a practical optimum (effort ~3–4 per stage). Beyond it, delay grows so much that inserting a buffer stage is faster — this optimum is precisely what Buffer Sizing and Inverter Chains computes.

If gate leakage were truly zero, would there be any static fan-out limit at all?

No DC/voltage-droop limit would exist (the

I_{O H} / I_{in}

ratio → ∞). The only remaining limit is dynamic: capacitance and therefore speed, which sets the timing budget in Propagation Delay and Timing.

At exactly

f = 1

(load equals the gate's own input cap), is an inverter's delay just its parasitic delay?

No — it is

d = g \cdot 1 + p = 1 + p

. The gate still spends one unit of effort delay driving a load equal to itself; only

f = 0

gives

d = p

What happens to

g_{N O R} = (2 N + 1) /3

N

grows very large — does the gate stay usable?

It grows without bound (~

2 N /3

), so a high-fan-in NOR becomes catastrophically slow. In practice CMOS avoids high-fan-in NORs entirely, using NAND-based trees instead.

Does fan-in affect the pull-up and pull-down equally in a NAND?

No. In a NAND the NMOS are in series (slow discharge) while the PMOS are in parallel (each sees full width). So fan-in degrades the pull-down (fall) path, not the rise — timing analysis must treat the two edges separately.

Connections

Logical Effort — the $d = g f + p$ law every item leans on.
RC Delay Model — source of the $0.69 R C$ and the linear cap dependence.
CMOS Static Logic Gates — why NAND stacks NMOS and NOR stacks PMOS.
Buffer Sizing and Inverter Chains — the real cure for large fan-out.
Transistor Sizing — widening to fight $R_{s t a c k}$ and where the cost migrates.
Propagation Delay and Timing — how these limits cap clock speed.