Visual walkthrough — Fan-in and fan-out limits

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Step 1 — A transistor is a switch that leaks like a resistor

WHAT. A CMOS gate output is either being pulled up to the supply voltage or pulled down to ground by a transistor. When that transistor is "on," it is not a perfect wire — it lets current through but resists it, like a narrow pipe.

WHY this picture. Before we can talk about time, we need to know what slows the electricity down. The answer is that the "on" transistor behaves like a resistor of value $R$. That single fact turns a messy semiconductor into something a 12-year-old can reason about: a pipe with a fixed narrowness.

WHAT IT LOOKS LIKE. Look at the figure. On the left is the real transistor symbol; on the right is the model we will use for the rest of the page — a plain resistor $R$. The width of the pipe is $R$: a wider transistor is a fatter pipe (smaller $R$), a narrower one is a thin pipe (bigger $R$).

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Step 2 — The loads a gate drives are a bucket of capacitance

WHAT. Every gate-input that our output wire touches is basically a tiny capacitor — a bucket that must be filled with charge to read "high" and emptied to read "low." Call one such input-bucket $C_g$.

WHY this picture. A transistor's job is not to move a light instantly; it is to charge a capacitor. If we know the total capacitance $C_L$ on the wire, and we know the pipe $R$, we can compute the fill time. So we must count buckets.

WHAT IT LOOKS LIKE. In the figure the driver's output wire fans out to $h$ downstream gate-inputs. Each is a bucket $C_g$, drawn in cyan. Buckets sitting on the same wire fill in parallel — their capacitances simply add. There is also the driver's own leftover "self" capacitance $C_{par}$ (amber), which is always there even with zero loads.

$$\underset{\text{total charge to fill}}{\underbrace{C_L}}=\underset{\text{how many loads}}{\underbrace{h}}\underset{\text{one input bucket}}{\underbrace{C_g}}+\underset{\text{driver’s own leftover}}{\underbrace{C_{par}}}$$

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Step 3 — Filling the bucket takes time: where "0.69 RC" is born

WHAT. Connect the pipe $R$ to the bucket $C_L$. The voltage on the bucket does not jump — it rises smoothly toward the supply $V_{DD}$ along a curve. We want the moment the voltage crosses the halfway mark $V_{DD}/2$, because that is when logic officially "flips."

WHY the exponential, and why halfway? The rate of filling is proportional to how empty the bucket still is (a nearly-full bucket fills slowly). "Rate proportional to the gap" is exactly the equation whose solution is the exponential $e^{-t/RC}$ — that is why the exponential appears and not some other curve. We pick the 50% point because gates measure delay input-to-output at the switching threshold, which sits near mid-supply.

WHAT IT LOOKS LIKE. The figure shows the rising curve. The dashed amber line is the halfway level. Reading off where the curve meets it:

$$V(t)=V_{DD}\left(1-e^{-t/RC}\right)$$

Set $V(t)=\frac{1}{2}{V}_{DD}$ and solve — the $V_{DD}$ cancels:

$$\frac{1}{2}=1-e^{-t/RC}\Rightarrow e^{-t/RC}=\frac{1}{2}\Rightarrow \frac{t}{RC}=\ln 2=0.693\dots$$ $$\boxed{t_{pd}=0.69R{C}_L}$$

Term by term: $t_{pd}$ = the delay we measure, $R$ = pipe narrowness (Step 1), $C_L$ = bucket size (Step 2), and $0.69=\ln 2$ is not magic — it is where a rising exponential crosses its own halfway line.

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Step 4 — Strip the units: turn $RC$ into $d=gf+p$

WHAT. The raw $0.69R{C}_L$ carries ugly units (ohms × farads = seconds). We want a dimensionless delay so that inverters, NANDs and NORs can be compared on one axis. We do this by measuring delay in multiples of one fixed reference delay $\tau$.

WHY normalize. A designer does not care that a gate takes "17 picoseconds" — that changes with every fabrication process. They care "how many inverter-delays is that?" Dividing out $\tau$ gives a number that survives across chips. This is the whole point of Logical Effort.

Define the reference $\tau$ first. Take one reference inverter: on-resistance $R_{ref}$ and input capacitance $C_{in,ref}$. The natural unit of delay is what it takes such an inverter to drive one identical copy of itself:

$$\tau =0.69R_{ref}{C}_{in,ref}$$

Here $R_{ref}$ = the pipe-width $R$ of the unit reference inverter, and $C_{in,ref}$ = the capacitance seen looking into one of its inputs. Every delay from now on is written as $d=t_{pd}/\tau$ — a pure number, "how many reference-inverter delays."

Now name the two capacitances we compare. For any gate:

• $C_{in}$ = the capacitance looking into this gate's own input (the bucket the previous stage must fill).
• $C_{out}$ = the total capacitance this gate drives on its output $=C_L$ from Step 2 $=h{C}_g+C_{par}$.

WHAT IT LOOKS LIKE. The figure splits the RC product into two independent knobs. Divide $t_{pd}=0.69R{C}_{out}$ by $\tau =0.69R_{ref}{C}_{in,ref}$ and insert $C_{in}$ (multiply and divide by it):

$$d=\frac{0.69R{C}_{out}}{0.69R_{ref}{C}_{in,ref}}=\underset{g}{\underbrace{\frac{R}{R_{ref}}\cdot \frac{C_{in}}{C_{in,ref}}}}\cdot \underset{f}{\underbrace{\frac{C_{out}}{C_{in}}}}$$

That last split defines the two efforts, and adding the load-independent parasitic term gives:

$$\underset{\text{delay in }\tau }{\underbrace{d}}=\underset{\begin{array}{c}\text{logical effort}\end{array}}{\underbrace{g}}\cdot \underset{\begin{array}{c}\text{electrical effort}\\ =C_{out}/C_{in}\end{array}}{\underbrace{f}}+\underset{\begin{array}{c}\text{parasitic delay}\end{array}}{\underbrace{p}}$$

• $g$ (logical effort) $=\frac{R{C}_{in}}{R_{ref}{C}_{in,ref}}$ — the product of how much worse this gate's pipe is ($R/R_{ref}$) and how much bigger its input bucket is ($C_{in}/C_{in,ref}$), for the same drive strength. A reference inverter has $R=R_{ref}$, $C_{in}=C_{in,ref}$, so $g=1$.
• $f$ (electrical effort = normalized fan-out) $=C_{out}/C_{in}$. This is how $h$ from Step 2 enters: $f=C_{out}/C_{in}=(h{C}_g+C_{par})/C_{in}$. For an inverter driving $h$ identical copies, $C_g=C_{in}$ and $C_{par}$ is folded into $p$, so $f\approx h$ — the raw load count.
• $p$ (parasitic delay) $=0.69R{C}_{par}/\tau$ — the $C_{par}$ term from Step 2 divided by $\tau$; the delay you pay even with zero load. For a reference inverter this is $p_{inv}$ (typically ≈ 1).

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Step 5 — Fan-out is the slide along the line (why loads hurt linearly)

WHAT. Keep the gate fixed, so $g$ and $p$ don't change. Now add more loads. Only $f$ grows. On the delay line, we simply slide right.

WHY linear. Buckets add in parallel (Step 2), so $C_{out}=h{C}_g+C_{par}$ grows in equal steps with each load $h$; since $f=C_{out}/C_{in}$ grows in step with $h$, and $d=gf+p$ is a straight line, equal steps in $h$ give equal steps in $d$. That is why the parent note says "double the loads ⇒ roughly double the effort delay."

WHAT IT LOOKS LIKE. The figure plots $d$ vs $f$ for an inverter ($g=1,p=1$). At $f=4$: $d=1\cdot 4+1=5$. At $f=8$: $d=1\cdot 8+1=9$. Two dots on one straight line — nearly double the delay for double the fan-out.

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Step 6 — Fan-in tilts and lifts the line (why inputs hurt worse)

WHAT. Now change the gate itself: stack $N$ transistors in series to make a NAND-$N$. This does two things at once — it raises the slope $g$ and the intercept $p$.

WHY $g$ grows — derive it. Recall $g=\frac{R{C}_{in}}{R_{ref}{C}_{in,ref}}$. For a NAND-$N$ we insist the pull-down path drive as strongly as the reference inverter's single NMOS. But now $N$ NMOS sit in series, so their resistances add: to match one unit NMOS we must widen each of the $N$ series NMOS by a factor $N$ (a fatter pipe cancels the $N\times$ series resistance). The PMOS pull-ups are in parallel (only one needs to conduct), so each stays at the inverter's PMOS width, which for matched CMOS is $2$ units (PMOS ~2× wider to fix mobility). One input therefore touches one NMOS of width $N$ and one PMOS of width $2$:

$$C_{in}^{\text{NAND-}N}\propto \underset{\text{series NMOS, widened}}{\underbrace{N}}+\underset{\text{parallel PMOS}}{\underbrace{2}}=N+2,C_{in,ref}^{\text{inv}}\propto \underset{\text{NMOS}}{\underbrace{1}}+\underset{\text{PMOS}}{\underbrace{2}}=3$$

With drive matched ($R=R_{ref}$ by the widening), $g$ is just the input-capacitance ratio:

$$g_{\text{NAND-}N}=\frac{C_{in}}{C_{in,ref}}=\frac{N+2}{3}$$

For a NOR-$N$ it is the PMOS that stack in series (NOR pulls up through series PMOS). Each series PMOS, already $2$ units for mobility, must be widened by $N$ → width $2N$; the parallel NMOS stay at $1$:

$$g_{\text{NOR-}N}=\frac{2N+1}{3}$$

WHY $p$ grows. Between the stacked transistors sit internal source/drain junctions, each a small parasitic bucket. Summing them, the parasitic delay scales as $p\approx N{p}_{inv}$, where $p_{inv}$ (defined in Step 4) is the parasitic delay of one reference inverter.

WHAT IT LOOKS LIKE. The figure overlays three lines for the same load axis: inverter, NAND-2, NAND-4. As $N$ rises the line gets steeper (bigger $g$) and starts higher (bigger $p$). Delay grows super-linearly in $N$ because two things worsen together.

$$g_{\text{NAND-}N}=\frac{N+2}{3},g_{\text{NOR-}N}=\frac{2N+1}{3},p\approx N{p}_{inv}$$

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Step 7 — The degenerate cases: read the line at its ends

WHAT. A derivation is only trustworthy if it survives the extremes. Check the two edges of the delay line.

WHY. If the formula misbehaves at $f=0$ or as $f\to \infty$, we'd have missed physics. It doesn't — and each end teaches a design rule.

WHAT IT LOOKS LIKE. The figure marks both ends of the line.

• Zero fan-out, $f=0$ (output drives nothing external): $d=g\cdot 0+p=p$. Delay does not hit zero — you still pay the parasitic $p$ from the driver's own $C_{par}$. This is the line's intercept, the floor.
• Huge fan-out, $f\to \infty$: $d\approx gf$ — the line rockets up with slope $g$. No cliff, just unbounded slowness. This is why a "fan-out limit" is a chosen speed budget, not a physical wall.
• The current-based (DC) limit — a different fan-out limit. Besides speed, an output must hold its logic "high" voltage above a guaranteed level while feeding every load. Two symbols capture this: $I_{OH}$ = the current the driver can source out of its output while still counting as "high"; $I_{in}$ = the small current each downstream input draws (leaks) from that node. If the loads collectively pull more than the driver can supply, the high voltage sags below spec, so the DC fan-out limit is $\lfloor I_{OH}/I_{in}\rfloor$. In older TTL logic, each input sinks a real $I_{in}$, so this current limit bites first. In pure CMOS an input is an insulated gate: $I_{in}\approx 0$, so $\lfloor I_{OH}/I_{in}\rfloor \to \infty$ — the DC limit is effectively infinite and the binding constraint is the capacitance/speed limit from this very line.

Recall Check: what is the delay of a gate driving nothing?

Not zero. ::: $d=p$ (the parasitic intercept), because the driver's own $C_{par}$ still must be charged.

Recall Check: in pure CMOS, which fan-out limit binds — current or speed?

Speed (capacitance). ::: Because $I_{in}\approx 0$, the current limit $\lfloor I_{OH}/I_{in}\rfloor$ is essentially infinite; only the $d=gf+p$ speed cost matters.

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The one-picture summary

WHAT everything reduces to. One straight line $d=gf+p$. Fan-out slides you along it (linear cost). Fan-in tilts the slope $g$ and lifts the intercept $p$ (super-linear cost). The line is born from filling one bucket through one pipe: $t_{pd}=0.69R{C}_L$, normalized by $\tau =0.69R_{ref}{C}_{in,ref}$.

Recall Feynman retelling of the whole walkthrough

A gate is a kid with a hose (the transistor = a pipe of width $R$). His job is to fill cups (each downstream input = a bucket $C_g$). Delay is the time to fill the cups halfway — and because a nearly-full cup fills slowly, that time follows a smooth curve whose halfway point is exactly $0.69RC$. To compare kids fairly we measure everyone in units of $\tau$: the time one reference kid needs to fill one standard cup. Line up more cups on the same wire — that's fan-out $f$ — and the fill time grows in a straight line: twice the cups, roughly twice the wait. Now instead make the kid pass water down a line of kids before it reaches the cup — that's fan-in, $N$ transistors in series: the line is $N$ times more resistive (so we fatten each kid, which grows the cup the previous stage must fill → bigger $g$), and puddles collect between each kid (parasitic junction caps → bigger $p$). Two hits, worse than fan-out. One more subtlety: filling (rise, through PMOS) and draining (fall, through NMOS) use different-strength kids, so we pre-widen the weaker PMOS to keep both directions equal. That is the entire chapter in one line: $d=gf+p$; slide it with fan-out, tilt-and-lift it with fan-in.

Connections

• RC Delay Model — Step 3, the origin of $0.69RC$.
• Logical Effort — Step 4, the $d=gf+p$ normalization.
• CMOS Static Logic Gates — Step 6, why NAND stacks NMOS and NOR stacks PMOS.
• Transistor Sizing — Step 6, widening to fight $R_{stack}=NR$.
• Buffer Sizing and Inverter Chains — Step 5, fixing large fan-out.
• Propagation Delay and Timing — where this line sets the clock.