Fan-in and fan-out limits: Exercises — Hardware deep dive

Level 1 — Recognition

Recall Solution L1.1

(a) Fan-in = number of inputs = 3 (three NMOS stacked in series in the pull-down net). (b) Fan-out counts the loads, not the inputs. The output drives $5$ inputs, so total load $C_{o u t} = 5 C_{g}$ . $f = \frac{C _{o u t}}{C _{in}} = \frac{5 C _{g}}{3 C _{g}} = \frac{5}{3} \approx 1.667$ Notice fan-out is not simply "5" here — it is 5 relative to this gate's own input size. A wider gate with the same 5 loads would have a smaller $f$ .

Recall Solution L1.2

A NOR output is high only when all inputs are low, so the pull-up must be all PMOS in series → the PMOS pull-up carries the 4-transistor stack. This matters because PMOS carriers (holes) have roughly half the mobility of NMOS carriers (electrons), so a PMOS must be ~2× wider for the same drive. That is exactly why NOR's logical effort $g = \frac{2 N + 1}{3}$ carries the " $2 N$ " penalty. See CMOS Static Logic Gates.

Level 2 — Application

Recall Solution L2.1

Step — electrical effort. 6 equal loads on an equal-size driver ⇒ $f = 6$ . Why: each load equals the input cap, six in parallel. Step — plug the law. $d = g f + p = 1 \cdot 6 + 1 = 7 τ$ . Double the loads to 12 and $d = 13 τ$ — nearly double: delay is linear in fan-out.

Recall Solution L2.2

$d = g f + p = \frac{4}{3} \cdot 4 + 2 = \frac{16}{3} + 2 = \frac{22}{3} \approx 7.33 τ$ Compare an inverter at the same $f = 4$ : $d = 1 \cdot 4 + 1 = 5 τ$ . The NAND is slower both because $g > 1$ (steeper slope) and $p > 1$ (higher offset).

Recall Solution L2.3

Origin of 0.69. The output rises as $V (t) = V_{D D} (1 - e^{- t / R C})$ . The 50% crossing solves $0.5 = 1 - e^{- t / R C}$ ⇒ $e^{- t / R C} = 0.5$ ⇒ $t = R C ln 2 = 0.6931 R C$ . Number. $t_{p d} = 0.69 \times (10 \times 1 0^{3}) \times (20 \times 1 0^{- 15}) = 0.69 \times 2.0 \times 1 0^{- 10} = 1.38 \times 1 0^{- 10} s = 138 ps$ .

Level 3 — Analysis

Recall Solution L3.1

NAND-2: $d = \frac{4}{3} \cdot 4 + 2 = \frac{22}{3} \approx 7.33 τ$ .
NAND-4: $d = 2 \cdot 4 + 4 = 12 τ$ .
Ratio $= 12/ \frac{22}{3} = \frac{36}{22} = \frac{18}{11} \approx 1.64$ . Fan-in raised both $g$ (slope: $\frac{4}{3} \to 2$ ) and $p$ (offset: $2 \to 4$ ), so the same load costs ~64% more delay. This is why we split large gates into trees (next level). See Transistor Sizing.

Recall Solution L3.2

NAND-3: $d = \frac{5}{3} \cdot 3 + 3 = 5 + 3 = 8 τ$ .
NOR-3: $d = \frac{7}{3} \cdot 3 + 3 = 7 + 3 = 10 τ$ . The NOR is $10/8 = 1.25 \times$ slower at identical fan-in and load, purely because it stacks weak PMOS. Rule of thumb: NOR is poorer — prefer NAND logic in CMOS.

Recall Solution L3.3

Step. Output current splits among loads; to keep the high level valid, $N \cdot I_{in} \leq I_{O H}$ . $N_{ma x} = ⌊ \frac{I _{O H}}{I _{in}} ⌋ = ⌊ \frac{4}{0.2} ⌋ = 20 loads$ Pure CMOS: gate leakage $I_{in} \approx 0$ , so this DC limit is essentially infinite — the real limit becomes capacitive (speed), not current. The current limit only bites at TTL/interface boundaries.

Level 4 — Synthesis

Recall Solution L4.1

Focus on the fan-in-loaded stage at $f = 4$ .

8-input NAND: $d = \frac{10}{3} \cdot 4 + 8 = \frac{40}{3} + 8 = \frac{64}{3} \approx 21.3 τ$ .
2-input NAND: $d = \frac{4}{3} \cdot 4 + 2 = \frac{22}{3} \approx 7.33 τ$ per stage. A balanced tree reaching 8 inputs needs $lo g_{2} 8 = 3$ levels of 2-input gates, roughly $3 \times 7.33 \approx 22 τ$ end-to-end — comparable to a single 8-NAND for one stage, but the tree's stages each drive light, well-sized loads and can be pipelined/buffered, whereas the monolithic 8-NAND's $8 R$ series resistance and $p = 8$ cannot be undone. As fan-in grows the monolithic delay climbs super-linearly; the tree grows only logarithmically in depth. See Buffer Sizing and Inverter Chains.

Recall Solution L4.2

(A) direct: $d = 1 \cdot 64 + 1 = 65 τ$ . (B) two equal stages: each stage $f = 8$ , so $d_{s t a g e} = 1 \cdot 8 + 1 = 9 τ$ , total $d = 2 \times 9 = 18 τ$ . Splitting a large effort into equal geometric-mean stages turns a linear $65 τ$ into a much smaller $18 τ$ . This is the whole idea of Buffer Sizing and Inverter Chains: the optimal per-stage effort is around $e \approx 4$ , so very large fan-outs want several stages.

Level 5 — Mastery

Recall Solution L5.1

(a) Doubling driver width halves its on-resistance, so its own electrical effort seen from its load halves in effect: the load $C_{o u t}$ is unchanged but $C_{in}$ doubles, so $f = C_{o u t} / C_{in}$ drops from $16$ to $8$ . New delay $d = 1 \cdot 8 + 1 = 9 τ$ (was $17 τ$ ). (b) But doubling this gate's width doubles its input capacitance, which is the load of the previous stage. The previous stage's $f$ doubles, adding delay upstream. Conclusion: fan-out fixes ripple backward. You cannot locally upsize without paying earlier in the chain — the correct answer is a jointly sized chain (equal effort per stage), not one greedy stage. See Propagation Delay and Timing.

Recall Solution L5.2

Per-stage delays with common $f = 2.29$ :

NOR-2: $d_{1} = \frac{5}{3} (2.29) + 2 = 3.817 + 2 = 5.817$
NAND-3: $d_{2} = \frac{5}{3} (2.29) + 3 = 3.817 + 3 = 6.817$
Inverter: $d_{3} = 1 (2.29) + 1 = 3.29$ $d_{p a t h} = 5.817 + 6.817 + 3.29 = 15.92 τ$ Read the anatomy: the slope terms ( $g f$ ) reward keeping stage effort near the optimum ( $\approx e$ ); the offset terms ( $p$ ) are the fixed cost of the chosen gates. The NOR and NAND cost more $p$ than an inverter — that is the fan-in tax showing up in the path budget. (Check: the logical-effort optimum verifies $F = G \cdot B \cdot H$ style bookkeeping in Logical Effort.)

Connections

Logical Effort — the $d = g f + p$ engine used in every problem here.
RC Delay Model — L2.3's origin of $0.69 R C$ .
CMOS Static Logic Gates — why NOR stacks PMOS (L1.2, L3.2).
Buffer Sizing and Inverter Chains — staging large fan-out (L4.2, L5.1).
Propagation Delay and Timing — path budgets (L5.2).
Transistor Sizing — widening vs input-cap tradeoff (L3.1, L5.1).

Exercises — Fan-in and fan-out limits