Gate is driven to VDD (s=1). We push a logic 1 (VDD) into node A and watch node B rise.
Node B rises from 0 toward VDD.
For the NMOS, the source is node B (the low side while it charges).
Transistor stays on while VGS=VDD−VB>Vtn.
It shuts off the instant VB=VDD−Vtn.
VB,maxNMOS=VDD−Vtn
Why this step? Because once VGS drops to exactly Vtn, there is no drive left — the channel vanishes, so B can never reach the full rail. That's the weak 1.
A PMOS turns on when VGS<Vtp (with Vtp<0), i.e. VSG>∣Vtp∣. Its "source" is the high terminal. If you try to pass a 0 through a PMOS, the output falls only until:
VB,minPMOS=∣Vtp∣
Why this step? Same self-throttling: as B falls, the PMOS's VSG shrinks; it dies at ∣Vtp∣. That's the weak 0.
Put them together: when passing a 1, the PMOS carries it to the full rail; when passing a 0, the NMOS carries it to ground. Whatever the value, at least one transistor is strong. That is the entire justification for the transmission gate.
What voltage does an NMOS pass-transistor output settle at when passing VDD?
What signals drive the two gates of a TG?
Why is the ON resistance of a TG roughly voltage-independent?
Answers: 1) It self-shuts when VGS=Vtn, so output stops at VDD−Vtn. 2) VDD−Vtn. 3) s to NMOS, sˉ to PMOS (complementary). 4) NMOS and PMOS weaken at opposite rails; their parallel combination stays roughly flat.
Recall Feynman: explain to a 12-year-old
Imagine a water pipe with a valve. One kind of valve (NMOS) can drain water out great, but when you try to fill the tank it stops a little short of the top. The other valve (PMOS) fills to the very top but can't quite empty the last bit. So we put both valves side by side and use them together: whenever you fill, the good-filler does the job; whenever you empty, the good-emptier does it. Now the tank always goes fully full and fully empty. That's a transmission gate — a smart double valve for electricity.
Dekho, ek single MOSFET switch ki tarah use karna tempting hai, par woh perfect nahi hota. NMOS strong 0 to nicely pass karta hai, lekin jab aap 1 (yaani VDD) pass karte ho to output sirf VDD−Vtn tak hi pahunchta hai — is ko "weak 1" bolte hain. Reason simple hai: NMOS tabhi ON rehta hai jab VGS>Vtn, aur output rise hote hi source voltage badh jaata hai, to VGS girta jaata hai aur transistor khud ko band kar leta hai. PMOS ka opposite problem hai — woh strong 1 pass karta hai par 0 sirf ∣Vtp∣ tak.
To solution kya? Dono ko parallel me jodo — yahi transmission gate hai. Jab logic 1 pass karna ho, PMOS full rail tak le jaata hai; jab logic 0 pass karna ho, NMOS ground tak le jaata hai. Matlab jo bhi value bhejo, koi ek transistor hamesha strong hota hai, aur output full swing milta hai — no threshold loss.
Ek important baat: dono gates ko complementary signals do — NMOS ko s, PMOS ko sˉ. Agar galti se dono ko same signal de diya to ek transistor hamesha OFF reh jaayega. Aur yaad rakho TG bidirectional switch hai, amplifier nahi — signal restore nahi karta, isliye lambi TG chains me beech me inverter/buffer daalte hain.
Practical me TG bahut jagah use hota hai: 2:1 multiplexer, latches/flip-flops ke feedback loop, compact XOR gates, aur analog sample-and-hold switches. Mnemonic yaad rakho: "N loves the floor, P loves the ceiling" — NMOS strong 0, PMOS strong 1, dono milke poora range cover.
