Transmission gates: Worked examples — Hardware deep dive

This page is the exhaustive drill room for Transmission gates. We take every kind of situation a transmission gate (TG) problem can hand you — passing a 1, passing a 0, the single-transistor failures, the degenerate "what if the thresholds are huge" case, resistance in parallel, a real MUX, and an exam twist — and grind through each one with forecasts, steps, and verifications.

Before we start, two facts everything below rests on.

An NMOS (the transistor that likes the floor) conducts only while its gate-to-source voltage clears a positive threshold $V_{t n}$ ; a PMOS (likes the ceiling) conducts only while its source-to-gate voltage clears $∣ V_{tp} ∣$ . If either of those terms is new, read MOSFET threshold voltage first — that note builds them from zero.

Intuition One extra effect that makes the weak levels

worse: the body effect The threshold $V_{t n}$ we quote is the value when the transistor's source sits at the same voltage as its substrate (body), usually ground. In a pass transistor the source is node B, and as B lifts off ground the source-to-body voltage $V_{S B}$ grows. A larger $V_{S B}$ raises the effective threshold — this is the body effect (back-gate bias). So the real weak-1 cutoff is not fixed at $V_{D D} - V_{t n 0}$ but at $V_{D D} - V_{t n} (V_{S B})$ with $V_{t n} (V_{S B}) > V_{t n 0}$ : the NMOS shuts off even earlier, giving an even weaker 1. The mirror statement holds for the PMOS weak-0 as B falls. We use the fixed-threshold formulas below (the standard textbook model); just remember the true drop is always a little worse than these numbers, which is one more reason to use a full TG.

The scenario matrix

Every TG problem is one of these cells. Our examples below cover all of them.

Cell	Situation	What can go wrong / what to watch
A. Pass a 1 through NMOS alone	logic high pushed through single NMOS	weak 1, stops at $V_{D D} - V_{t n}$
B. Pass a 0 through PMOS alone	logic low pushed through single PMOS	weak 0, stops at $∣ V_{tp} ∣$
C. Pass a 1 through full TG	PMOS rescues the high	full rail, no drop
D. Pass a 0 through full TG	NMOS rescues the low	full ground, no drop
E. Degenerate threshold	$V_{t n}$ or $∣ V_{tp} ∣$ nearly $= V_{D D}$	single transistor barely passes anything (both signs)
F. Parallel ON resistance	two resistors in parallel	smaller than either alone
G. Sign / complement error	same signal on both gates	one transistor stays OFF forever
H. Real-world word problem	2:1 MUX routing	exactly one TG ON, full-rail output
I. Exam twist	noise-margin / RC-delay reasoning	weak level eats the next gate's margin
J. Body-effect edge case	source lifts off substrate, $V_{t}$ grows	weak 1/0 is worse than the flat formula

Example 1 — Cell A: the weak 1 of a lone NMOS

Forecast: Guess before reading — will B reach the full 1.2 V, or fall short? By how much?

Identify the source. While B is low, the NMOS's source is node B (the lower terminal). Why this step? An NMOS's source is always the terminal at the lower voltage; the threshold condition $V_{GS} > V_{t n}$ is measured from there, so we must pin down which node is the source before writing any inequality.
Write the ON condition. Gate is at $V_{D D}$ , source is $V_{B}$ , so $V_{GS} = V_{D D} - V_{B}$ . The device conducts while $V_{D D} - V_{B} > V_{t n}$ . Why this step? This inequality is the entire self-throttling story — as $V_{B}$ climbs, $V_{GS}$ shrinks toward $V_{t n}$ .
Find the cutoff. Conduction dies the instant $V_{D D} - V_{B} = V_{t n}$ , i.e. $V_{B} = V_{D D} - V_{t n} = 1.2 - 0.35 = 0.85$ V. Why this step? Once $V_{GS} = V_{t n}$ the channel vanishes; no drive means B cannot rise further.

$V_{B, m a x} = V_{D D} - V_{t n} = 0.85 V$

Verify: The loss is exactly one threshold, $1.2 - 0.85 = 0.35 = V_{t n}$ ✓. Units: all volts ✓. This is the classic weak 1 described in Pass transistor logic. (Body effect, Example 9, makes the true value slightly below 0.85 V.)

Example 2 — Cell B: the weak 0 of a lone PMOS

Forecast: Will B reach 0 V, or stop above it?

Identify the source. For a PMOS, the source is the higher-voltage terminal. While B is being pulled down but still elevated, node B is the source. Why this step? PMOS threshold is measured source-to-gate; the source is the high side, the mirror image of the NMOS.
Write the ON condition. Gate at 0, source at $V_{B}$ , so $V_{S G} = V_{B} - 0 = V_{B}$ . Conducts while $V_{S G} > ∣ V_{tp} ∣$ , i.e. $V_{B} > 0.4$ V. Why this step? As B falls, $V_{S G}$ shrinks toward $∣ V_{tp} ∣$ — the PMOS throttles itself near the floor.
Find the cutoff. Conduction stops at $V_{B} = ∣ V_{tp} ∣ = 0.4$ V. Why this step? Below this, the channel is gone; B is stranded above ground.

$V_{B, m i n} = ∣ V_{tp} ∣ = 0.4 V$

Verify: B stops $0.4$ V above ground = one $∣ V_{tp} ∣$ ✓. This is the weak 0 — a PMOS "loves the ceiling," so it can't finish the floor.

Example 3 — Cells C & D: the full TG kills both drops

Forecast: In each case, which of the two transistors does the last stretch of the journey?

(a) Pass a 1. The NMOS stalls at $0.85$ V (Example 1). But the PMOS is ON and its source is the $V_{D D}$ input side, so its $V_{S G}$ stays large all the way up. Why this step? A passed 1 climbs toward the rail; the PMOS strengthens as B rises, exactly where the NMOS weakens.
PMOS finishes the climb. It drives B to the full rail: $V_{B} = V_{D D} = 1.2$ V. Why this step? No threshold gates a PMOS at the top — "P loves the ceiling."
(b) Pass a 0. The PMOS stalls at $0.4$ V (Example 2), but the NMOS is ON and pulls B all the way to ground: $V_{B} = 0$ V. Why this step? The NMOS strengthens near the floor — "N loves the floor."

$V_{B}^{(1)} = 1.2 V, V_{B}^{(0)} = 0 V$

Verify: Full swing $1.2 - 0 = 1.2$ V $= V_{D D}$ — zero threshold loss ✓. The parallel partner covered exactly the rail the lone device could not. This is the whole reason the TG exists (CMOS inverter is what generates the complementary $\overset{s}{ˉ}$ ).

Example 4 — Cell E: degenerate thresholds (both signs, limiting case)

Forecast: Is a 0.9 V threshold "a small annoyance" or "a disaster" — and does the PMOS side behave symmetrically?

(a) NMOS weak-1. $V_{B, m a x} = V_{D D} - V_{t n} = 1.0 - 0.9 = 0.1$ V, i.e. $0.1/1.0 = 10%$ of the rail. Why this step? The Example-1 result holds for any values; a tenth-of-rail "high" is clearly unusable as a logic 1.
(b) PMOS weak-0 (the symmetric case). $V_{B, m i n} = ∣ V_{tp} ∣ = 0.85$ V, i.e. the "low" is stranded only $1.0 - 0.85 = 0.15$ V below the rail — barely $15%$ of the way down. Why this step? The PMOS story mirrors the NMOS one; a near- $V_{D D}$ $∣ V_{tp} ∣$ makes the weak-0 almost useless, so both signs degenerate, not just the high.
(c) Both limits. As $V_{t n} \to V_{D D}$ , $V_{B, m a x} = V_{D D} - V_{t n} \to 0$ — the NMOS passes no 1 at all. As $∣ V_{tp} ∣ \to V_{D D}$ , $V_{B, m i n} = ∣ V_{tp} ∣ \to V_{D D}$ — the PMOS passes no 0 at all (it can't move B off the rail). Why this step? It maps the boundary of both formulas: each degenerate threshold erases its own weak level entirely.

$V_{B, m a x} = 0.1 V (10%), V_{B, m i n} = 0.85 V, lim_{V_{t n} \to V_{D D}} V_{B, m a x} = 0, lim_{∣ V_{tp} ∣ \to V_{D D}} V_{B, m i n} = V_{D D}$

Verify: NMOS: $1.0 - 0.9 = 0.1$ ✓, fraction $0.1$ ✓. PMOS: weak-0 stuck at $0.85$ , i.e. $1.0 - 0.85 = 0.15$ V below rail ✓. Limits: $V_{D D} - V_{D D} = 0$ ✓ and $∣ V_{tp} ∣ = V_{D D}$ ✓ — both monotone toward "passes nothing."

Example 5 — Cell F: parallel ON resistance (with figure)

Forecast: Will the combined resistance be near 6 k, near 9 k, or below both?

The figure below draws the ON transmission gate between node A (left dot) and node B (right dot). The magenta top path is the NMOS modelled as $R_{n} = 6 k Ω$ ; the violet bottom path is the PMOS modelled as $R_{p} = 9 k Ω$ . Both start at A and both end at B — that is what "in parallel" looks like: two separate roads between the same two towns. The green arrow across the middle marks the single equivalent resistance $R_{T G} = 3.6 k Ω$ , and the green caption reminds you it sits below both individual resistors.

Figure (alt-text): a transmission gate drawn as node A on the left joined to node B on the right by two parallel resistor paths — a magenta top path labelled $R_{n} = 6 k Ω$ (NMOS) and a violet bottom path labelled $R_{p} = 9 k Ω$ (PMOS) — with a green arrow through the middle labelled $R_{T G} = \frac{6 \cdot 9}{6 + 9} = 3.6 k Ω$ and the note "below BOTH resistors." If the image fails to load, read this description in its place.

Parallel formula. $R_{T G} = \frac{R _{n} R _{p}}{R _{n} + R _{p}} = \frac{6 \cdot 9}{6 + 9} = \frac{54}{15} = 3.6 k Ω$ . Why this step? Two resistors between the same two nodes (the two roads in the figure) carry current together, so conductances add — the combined resistance is always below the smaller one.
Compare. $3.6 < 6$ and $3.6 < 9$ ✓ — smaller than both, exactly as the green arrow claims. Why this step? This is the sanity check that guarantees no arithmetic slip: a parallel combination can never exceed either resistor.
RC estimate. $τ = R_{T G} C = 3600 Ω \times 50 \times 1 0^{- 15} F = 1.8 \times 1 0^{- 10} s = 180 ps$ . Why this step? Charging a load through a switch is a first-order RC process; a smaller $R_{T G}$ means a smaller $τ$ , i.e. faster. See RC delay in interconnects.

$R_{T G} = 3.6 k Ω, τ = 180 ps$

Verify: $3.6 \cdot 15 = 54 = 6 \cdot 9$ ✓. $τ$ units: $Ω \cdot F = s$ ✓; $3600 \times 5 \times 1 0^{- 14} = 1.8 \times 1 0^{- 10}$ s ✓.

Example 6 — Cell G: the complement-error trap

Forecast: Guess: does the gate work, half-work, or never work?

Case $s = 1$ . NMOS gate $= 1 > 0$ ⇒ NMOS ON. PMOS gate $= 1$ ; a PMOS needs gate LOW to turn on, so PMOS is OFF. Why this step? NMOS and PMOS turn on with opposite gate polarities; we must test each separately.
Case $s = 0$ . NMOS gate $= 0$ ⇒ NMOS OFF. PMOS gate $= 0$ ⇒ PMOS ON. Why this step? Now the roles flip — but still only one device is ever on.
Conclusion. In neither state are both ON together, so you never get the full-rail, low-resistance TG behaviour. The correct wiring is NMOS gate $= s$ , PMOS gate $= \overset{s}{ˉ}$ . Why this step? Complementary drive is what makes both conduct simultaneously.

$Correct: NMOS \leftarrow s, PMOS \leftarrow \overset{s}{ˉ} (complementary)$

Verify: With correct wiring at $s = 1$ : NMOS gate $= 1$ (ON), PMOS gate $= \overset{s}{ˉ} = 0$ (ON) — both ON ✓, the only combination that gives strong 0 and strong 1.

Example 7 — Cell H: real-world 2:1 MUX

Forecast: What is $Y$ for $s = 0$ ? For $s = 1$ ? Any voltage drop?

Wire two TGs. TG $_{A}$ : NMOS gate $= \overset{s}{ˉ}$ , PMOS gate $= s$ (ON when $s = 0$ ). TG $_{B}$ : NMOS gate $= s$ , PMOS gate $= \overset{s}{ˉ}$ (ON when $s = 1$ ). Tie both outputs to $Y$ . Why this step? Complementary control means exactly one TG conducts at a time — no bus fight (see Multiplexers).
$s = 0$ : route $A = 1.8$ V. TG $_{A}$ ON, TG $_{B}$ OFF. Because it's a full TG passing a 1, the NMOS alone would stall at $V_{D D} - V_{t n} = 1.8 - 0.4 = 1.4$ V — but the PMOS partner carries the last stretch to the rail, so $Y = A = 1.8$ V with no $V_{t n}$ drop. Why this step? This is Example 3(a) with these exact thresholds — the $0.4$ V NMOS drop is precisely what the PMOS erases.
$s = 1$ : route $B = 0$ V. TG $_{B}$ ON, TG $_{A}$ OFF. The PMOS alone would stall at $∣ V_{tp} ∣ = 0.45$ V, but the NMOS partner pulls B all the way down, so $Y = B = 0$ V with no $∣ V_{tp} ∣$ drop. Why this step? Example 3(b) with $∣ V_{tp} ∣ = 0.45$ V — the NMOS cancels the would-be $0.45$ V floor error.

$Y = {A = 1.8 V, B = 0 V, s = 0 s = 1$

Verify: Weak levels a single transistor would give: $1.8 - 0.4 = 1.4$ V (high) and $0.45$ V (low). Full TG restores them to $1.8$ V and $0$ V — the $0.4$ V and $0.45$ V errors both vanish ✓. Exactly one TG ON per case (no contention) ✓. Truth: $Y = \overset{s}{ˉ} A + s B$ , the textbook 2:1 MUX equation ✓.

Example 8 — Cell I: exam twist (noise margin swallowed by a weak 1)

Forecast: Is the weak 1 still "clearly a 1" to the next stage, or dangerously close?

Weak-1 level. $V_{B} = V_{D D} - V_{t n} = 1.0 - 0.3 = 0.7$ V. Why this step? The next gate sees only this degraded high, not the full rail.
Margin check. Required $V_{I H} = 0.75$ V but arriving level is $0.7$ V. Margin $= 0.7 - 0.75 = - 0.05$ V — negative! Why this step? A negative margin means the "1" is below what the receiver reliably reads as high; the logic may misinterpret it or draw crowbar current.
TG fix. A full TG drives $V_{B} = V_{D D} = 1.0$ V, giving margin $1.0 - 0.75 = + 0.25$ V. Why this step? Restoring the rail restores a healthy positive margin — the exact motivation for using TGs over single pass transistors (Latches and flip-flops rely on this).

$weak-1 margin = - 0.05 V (fails), TG margin = + 0.25 V (safe)$

Verify: $0.7 - 0.75 = - 0.05$ ✓ (fails); $1.0 - 0.75 = 0.25$ ✓ (passes). Confirms the "weak 1 corrupts the next gate" warning from the parent note.

Example 9 — Cell J: body effect makes the weak 1 even weaker

Forecast: The flat formula says $0.7$ V. Will the body effect push the true value up, down, or leave it unchanged?

Naive value first. Ignoring body effect, $V_{B, m a x}^{naive} = V_{D D} - V_{t n 0} = 1.0 - 0.3 = 0.7$ V. Why this step? This is the baseline every earlier example used; we now correct it.
Iterate once. At $V_{S B} \approx 0.7$ V the raised threshold is $V_{t n} = 0.3 + 0.4 (0.7 + 0.7 - 0.7) = 0.3 + 0.4 (1.1832 - 0.8367) = 0.3 + 0.1386 = 0.4386$ V. Why this step? A lifted source raises $V_{t}$ ; plugging the naive cutoff in gives a first correction — the source can't actually reach $0.7$ V because the transistor now needs $0.44$ V of $V_{GS}$ , not $0.3$ V.
Re-solve the cutoff. Cutoff is where $V_{D D} - V_{B} = V_{t n} (V_{B})$ . Using the raised threshold, $V_{B, m a x} \approx V_{D D} - 0.4386 = 1.0 - 0.4386 = 0.561$ V. Why this step? The self-consistent answer is lower than the naive $0.7$ V — the weak 1 is weaker than the flat formula predicts, exactly the real-world edge case.

$V_{B, m a x}^{naive} = 0.70 V \Rightarrow V_{B, m a x}^{body} \approx 0.56 V (lower)$

Verify: $1.4 \approx 1.1832$ , $0.7 \approx 0.8367$ , difference $\approx 0.3465$ ; $0.4 \times 0.3465 = 0.1386$ ; $V_{t n} = 0.4386$ V $> V_{t n 0}$ ✓ (threshold rose). $1.0 - 0.4386 = 0.5614 < 0.70$ ✓ — the true weak 1 is below the naive one, and a full TG (PMOS partner) is what wipes out both the nominal and the body-effect loss.

Active recall

Recall Which transistor finishes the job when passing a 1? A 0?

Passing a 1 ::: the PMOS drives to the full rail (N stalls at $V_{D D} - V_{t n}$ ). Passing a 0 ::: the NMOS drives to ground (P stalls at $∣ V_{tp} ∣$ ).

Recall Why is

$R_{T G}$ always below both $R_{n}$ and $R_{p}$ ? Because they're in parallel — conductances add, so the combined resistance is smaller than the smaller resistor.

Recall How does the body effect change the weak 1?

As node B rises, $V_{S B}$ grows, which raises $V_{t n}$ , so the NMOS cuts off earlier — the weak 1 ends up below the flat $V_{D D} - V_{t n 0}$ estimate.

Connections

Transmission gates — the parent this drill expands.
Pass transistor logic — Cells A, B, E, J (single-device weaknesses).
MOSFET threshold voltage — where every drop, and the body effect, come from.
CMOS inverter — generates $\overset{s}{ˉ}$ and restores levels (Cell I).
Multiplexers — Cell H.
Latches and flip-flops — TG in feedback paths.
RC delay in interconnects — Cell F timing.

Weak-1 level of a lone NMOS pass transistor?

V_{D D} - V_{t n}

(and even lower once body effect raises

V_{t n}

Weak-0 level of a lone PMOS pass transistor?

∣ V_{tp} ∣

Parallel ON resistance of a TG?

R_{T G} = \frac{R _{n} R _{p}}{R _{n} + R _{p}}

, always below both.

What does the body effect do to a pass transistor's weak level?

Rising source voltage increases

V_{S B}

, which raises the threshold, so the transistor cuts off earlier and the weak 1/0 is worse.