Exercises — Transmission gates

• NMOS passes a strong 0 (down to $0$ V) but only a weak 1.
• PMOS passes a strong 1 (up to $V_{DD}$) but only a weak 0. Mnemonic: "N loves the floor, P loves the ceiling."

The PMOS gate is driven by $\bar{s}$ (the complement, defined above). The gate is ON when $s=1,\bar{s}=0$ — then both transistors conduct. Same signal on both would leave one transistor permanently off.

False. A TG is bidirectional, meaning it has no dedicated input or output: both terminals are shared source/drain nodes, so current can flow either way through the closed switch. It is a switch, not an amplifier — it does not decide a direction and it does not restore the signal.

The NMOS self-shuts when $V_{GS}=V_{tn}$. Its source is the output node (the low side while charging), so $V_{B,\max }=V_{DD}-V_{tn}=1.8-0.4=1.4\text{ V}.$ Loss versus the rail $=1.8-1.4=0.4$ V $=V_{tn}$. This is the weak 1.

The PMOS self-shuts when $V_{SG}=|V_{tp}|$. Its source is the high terminal, so as the output falls it stalls at $V_{B,\min }=|V_{tp}|=0.45\text{ V}.$ This is the weak 0.

The PMOS is the strong device for a passed 1. Its source is at $V_{DD}$; it keeps conducting all the way, so $V_B=V_{DD}=1.8\text{ V}(\text{no threshold loss}).$ The NMOS alone would have stopped at $1.4$ V; the PMOS finishes the job to the full rail.

Parallel resistors: $R_{TG}=\frac{R_n{R}_p}{R_n+R_p}=\frac{5\cdot 8}{5+8}=\frac{40}{13}\approx 3.08\text{ k}\Omega .$ Smaller than either device — a TG is a lower-resistance switch than a single transistor.

The drive that charges $C$ is set by the overdrive $V_{GS}-V_{tn}=(V_{DD}-V_B)-V_{tn}$. As $V_B$ rises this overdrive shrinks, so the current falls, so the slope of $V_B(t)$ flattens — an exponential-looking approach (look at the amber curve bending over). When $V_B=V_{DD}-V_{tn}=1.4$ V the overdrive hits zero: no drive, no more charging. The cyan dashed ceiling at $1.4$ V is never crossed. That is the geometric picture of the weak 1.

Near the top rail the NMOS overdrive collapses, so $R_n$ shoots up (cyan curve rising on the right). Near the bottom rail the PMOS overdrive collapses, so $R_p$ shoots up (white curve rising on the left). But the parallel combination $R_n\parallel R_p$ (amber) is dominated by whichever resistor is small: at every voltage at least one device is strong, so the amber curve stays low and nearly flat across the whole sweep. That is why a TG is a fairly voltage-independent switch.

Per-stage time constant $\tau =R_{TG}C=3000\times 4\times 10^{-15}=1.2\times 10^{-11}=12\text{ ps}$.

• Naive linear guess: $8\tau =96$ ps.
• Reality — where the quadratic comes from (Elmore sketch): label the nodes $1,2,\dots ,n$ along the chain, each a capacitor $C$ fed through one resistor $R$. To charge node $k$'s capacitor, current must flow through every resistor upstream of it — that is $k$ resistors. So node $k$ contributes a delay term $RC\cdot k$ (its cap seen through $k$ resistances). The Elmore delay is the sum of all these terms: $t\approx {\sum }_{k=1}^{n}kRC=RC\frac{n(n+1)}{2}.$ The $\sum k=\frac{n(n+1)}{2}$ is what turns a linear chain into a quadratic delay. Numerically, with $\tau =RC=12$ ps and $n=8$: $t\approx \frac{8\cdot 9}{2}\times 12=36\times 12=432\text{ ps}.$ So the delay balloons quadratically, not linearly — the reason we insert buffers (CMOS inverters) periodically, per RC delay in interconnects.

• TG1 passes $A$. It must be ON when $s=0$. So its NMOS gate = $\bar{s}$ and its PMOS gate = $s$.
• TG2 passes $B$. It must be ON when $s=1$. So its NMOS gate = $s$ and its PMOS gate = $\bar{s}$.
• Tie both TG outputs to the node $Y$. Why no fight: exactly one TG is ON for any value of $s$ (they use complementary conditions), so only one input ever drives $Y$. Why no restoring inverter for logic levels: each TG delivers a full-rail output (0 and 1), unlike a single pass transistor. See Multiplexers.

• Forward TG (ON when $\varphi =1$): connects input $D$ to the storage node $Q$. When $\varphi =1$ the latch is transparent — $Q$ follows $D$.
• Feedback TG (ON when $\varphi =0$): closes a loop through an inverter pair back onto $Q$. When $\varphi =0$ the latch holds — the forward TG is off, the feedback TG regenerates the stored value. The two TGs are driven by opposite phases so exactly one path is active at a time (no fight, no float). This is the classic TG-based D latch of Latches and flip-flops.

The NMOS delivers $V_{DD}-V_{tn}$. This reaches $0$ V exactly when $V_{DD}=V_{tn}=0.4$ V — below that the NMOS passes nothing on a 1. Even well above it, the fraction $\frac{V_{DD}-V_{tn}}{V_{DD}}$ shrinks as $V_{DD}$ drops (e.g. at $V_{DD}=0.8$ V you only get $0.4$ V — half the rail). The full TG has no such threshold loss (PMOS finishes to the rail), so it becomes mandatory at low supplies. This is the low-voltage argument for using TGs over bare Pass transistor logic.

$V_{B,\max }=V_{DD}-V_{tn}=1.8-0.5=1.3\text{ V}.$ With body effect the weak 1 is even weaker ($1.3$ V vs. the $1.4$ V you'd get ignoring it). So ignoring body effect is optimistic — real single-NMOS pass gates deliver less than $V_{DD}-V_{tn0}$. Yet another reason the PMOS partner is needed. (See MOSFET threshold voltage for why a raised source lifts $V_{tn}$.)

The PMOS turns fully off for gate $>1.8-0.45=1.35$ V. The weak-1 level $1.4$ V is $1.4>1.35$, so the PMOS is just off — but only by a $0.05$ V margin. With body effect (L5.2) the level is $1.3$ V $<1.35$ V, so the PMOS stays partly ON: both transistors of the inverter conduct → static crowbar current wastes power continuously. This is the concrete cost of the weak 1, and precisely why a TG (delivering the full $1.8$ V) eliminates the leakage.

ON resistance $\propto \frac{1}{\mu (W/L)}$. To match $R_p=R_n$ at equal length, make ${\mu }_n{W}_n={\mu }_p{W}_p$, so $\frac{W_p}{W_n}=\frac{{\mu }_n}{{\mu }_p}\approx \mathrm{2.5.}$ Widen the PMOS $\sim 2.5\times$ to compensate its lower mobility. This gives a more voltage-independent, symmetric $R_{TG}$ across the sweep.