Transmission gates: Question bank — Hardware deep dive

Intuition How to use this page

Each line below is a trap: a statement or question that sounds reasonable but hides a subtlety. Cover the answer, commit to a judgement out loud, and justify it before revealing. If your reason matches the answer's reason — not just its yes/no — you understand the transmission gate. If you only got the verdict, you got lucky.

Every symbol here is built in the parent note. Quick refresher of the vocabulary:

$V_{D D}$ ::: the top supply rail, the highest voltage in the circuit (the "ceiling").
$V_{t n}$ ::: the NMOS threshold — the minimum gate-to-source voltage needed to turn an NMOS on. See MOSFET threshold voltage.
$∣ V_{tp} ∣$ ::: the magnitude of the PMOS threshold ( $V_{tp}$ itself is negative).
$s, \overset{s}{ˉ}$ ::: the two complementary control signals; $\overset{s}{ˉ}$ is the logical NOT of $s$ .
$R_{T G}$ ::: the ON-resistance of the whole gate (NMOS and PMOS resistances in parallel).

Intuition The one rule that unlocks every trap below — the moving source

Before you attempt the questions, fix this convention firmly, because most of the traps hinge on it. In a pass transistor neither terminal is wired to a supply, so we cannot label one "source" and one "drain" in advance. Instead:

For an NMOS, the source is whichever of its two terminals sits at the lower voltage at that instant.
For a PMOS, the source is whichever terminal sits at the higher voltage. As the passed node charges or discharges, its voltage moves, so which physical terminal counts as the source can swap mid-transition. The figure below fixes this picture; refer back to it whenever a question mentions "source". This is why the same NMOS is strong for 0s (source pinned low) but weak for 1s (source rides up with the output).

And keep this quantitative anchor beside it — passing a 1, the NMOS self-cuts when its source rises to $V_{D D} - V_{t n}$ ; passing a 0, the PMOS floors out at $∣ V_{tp} ∣$ . The picture below plots exactly where each device dies.

True or false — justify

An NMOS pass transistor passes a logic 0 all the way down to 0 V.

True. Here the input terminal is held at

0

V and node B starts high and is being pulled down. For an NMOS the source is the lower-voltage terminal — the

0

V input side — while B (the falling node) acts as the drain, so

V_{GS}

stays large and the device keeps conducting until B reaches ground. No throttling on the low side.

A PMOS alone can deliver a full-rail logic 1.

True. For a passed 1 the input is at

V_{D D}

, which is the PMOS's source (the higher-voltage terminal); its

V_{S G}

stays above

∣ V_{tp} ∣

all the way up, so it drives B to the full

V_{D D}

. That is exactly why the PMOS is the TG's "strong-1" partner.

In an ideal transmission gate the ON-resistance is exactly zero.

False. Each transistor is a small but finite resistor; even in parallel

R_{T G} = R_{n} R_{p} / (R_{n} + R_{p}) > 0

. It is low and roughly flat, not zero.

A TG in a long chain of

N

gates has the same effective

R_{T G}

delay as a single TG.

False. Each gate adds its own

R_{T G}

in series with node capacitance, so the RC delay grows with

N

— see RC delay in interconnects. That is why buffers are inserted along the chain.

Driving both gates of a TG with the same signal

s

turns both transistors on together.

False. NMOS wants gate

= 1

, PMOS wants gate

= 0

. A common

s

leaves one device permanently off, so you get at best a single-transistor pass gate with its threshold drop.

A transmission gate amplifies or restores the signal passing through it.

False. It is a passive bidirectional switch — a resistor when ON. It does not regenerate levels; that is the job of a following CMOS inverter buffer.

V_{t n} = 0

and

∣ V_{tp} ∣ = 0

, a single NMOS would be a perfect switch and the TG would be unnecessary.

True in principle. The whole defect is the threshold drop; with zero thresholds there is no weak 1 or weak 0. Real transistors have nonzero thresholds, so the TG remains necessary.

The two transistors in a TG share the same two source/drain terminals.

True. They sit in parallel between node A and node B; only their gate signals differ. That shared-terminal parallel wiring is what lets one device rescue the other.

A TG conducts current in only one direction, input to output.

False. It is bidirectional — there is no fixed input or output. Current flows whichever way the voltage difference pushes it.

Spot the error

"An NMOS passes a weak 1 because its channel resistance is too high near

V_{D D}

The real cause is not high resistance but cutoff: at

V_{B} = V_{D D} - V_{t n}

we get

V_{GS} = V_{t n}

, the channel vanishes entirely. It stops, it doesn't merely slow down.

"To fix the weak 1, add a second NMOS in parallel with the first."

Two NMOS in parallel both self-cut at

V_{D D} - V_{t n}

— you'd get the same weak 1, just lower resistance. You need a PMOS, the device whose strength is at the top rail.

"Passing a 1 through a TG, the NMOS carries it to

V_{D D}

and the PMOS helps a little."

Backwards near the top. The NMOS dies at

V_{D D} - V_{t n}

; it is the PMOS that carries the last stretch to the full rail. Near the top rail the PMOS is the strong device.

"Since a TG has near-zero resistance, chaining 20 of them adds no delay."

Each TG contributes finite

R_{T G}

and each node has capacitance, so RC delay accumulates along the chain. That is why buffers are inserted periodically — see RC delay in interconnects.

"A 2:1 MUX built from TGs needs a restoring inverter on its output to fix the logic level."

Not for the level — a TG gives full-rail outputs, so levels are clean. You may add a buffer for drive strength/delay, but not to repair a threshold drop that isn't there.

"The PMOS in a TG needs gate signal

s

because it must turn on with the NMOS."

It must turn on together, yes, but a PMOS turns on when its gate is low. So it needs

\overset{s}{ˉ}

, not

s

. "Together on" and "same gate voltage" are not the same thing here.

V_{tp}

is positive, so a PMOS passes a strong 0 down to

V_{tp}

V_{tp}

is negative; the PMOS's weak-0 floor is

∣ V_{tp} ∣

(a positive voltage above ground). Dropping the absolute value flips the sign wrongly.

Why questions

Why does the source of a pass transistor "move" instead of staying fixed?

In a pass transistor neither terminal is tied to a supply; the source is defined as the lower-voltage terminal (for NMOS). As the passed node charges, that terminal's voltage rises, so

V_{GS}

shrinks live — the device throttles itself.

Why does teaming NMOS and PMOS give a switch better than either alone?

They fail at opposite rails: NMOS weakens near

V_{D D}

, PMOS weakens near ground. In parallel, wherever one is dying the other is strong, so the pair covers the full 0-to-

V_{D D}

range and

R_{T G}

stays roughly flat.

Why does a TG's ON resistance stay roughly voltage-independent across the swing?

R_{n}

climbs toward the top rail while

R_{p}

climbs toward the bottom rail; their parallel combination is dominated by whichever is small, so the total stays low across the whole voltage range.

Why is a single NMOS acceptable for passing 0s but not for passing 1s?

Passing 0, its source is the low input, so

V_{GS}

stays large down to ground — strong 0. Passing 1, its source rises with the output, self-cutting at

V_{D D} - V_{t n}

— weak 1.

Why do TGs make especially clean multiplexers compared to Pass transistor logic with single transistors?

TGs pass both logic levels full-rail with no threshold loss, so the selected input arrives undistorted; single-transistor pass logic delivers a degraded 1 (or 0) that must be restored.

Why must the two control signals be complementary rather than independent?

To switch the whole gate as one unit: both transistors ON together (

s = 1, \overset{s}{ˉ} = 0

) or both OFF (

s = 0, \overset{s}{ˉ} = 1

). Independent signals could leave a half-open, undefined state.

Edge cases

What is the output of a full TG passing a 1 when

V_{D D} = 1.8

V_{t n} = 0.4

A full

1.8

V. The NMOS quits at

1.4

V but the PMOS carries the node to the rail with no threshold loss — that is the TG's whole point.

If a TG were built from two NMOS in parallel (no PMOS), what happens passing a 1?

Both self-cut at

V_{D D} - V_{t n}

, so the output is still a weak 1 at

V_{D D} - V_{t n}

. Lower resistance, same threshold defect — no rescue at the top rail.

At exactly

V_{B} = V_{D D} - V_{t n}

, what is the NMOS doing?

It is right at cutoff:

V_{GS} = V_{t n}

, the channel is just vanishing, drive current

\to 0

. In a real device conduction tapers smoothly, so this is the effective ceiling, not a hard cliff.

What voltage does a PMOS alone settle at when passing a 0, with

∣ V_{tp} ∣ = 0.45

It stops at

∣ V_{tp} ∣ = 0.45

V above ground — the weak 0 — because its

V_{S G}

collapses below

∣ V_{tp} ∣

once the node falls that far.

What is the intended OFF state of a TG, and what is node B then?

OFF is

s = 0, \overset{s}{ˉ} = 1

: the NMOS gate is low (off) and the PMOS gate is high (off), so both are non-conducting and node B is floating / high-impedance, held only by leakage and node capacitance. This isolation is what makes TGs useful in Latches and flip-flops and tri-state buses.

What actually happens if a glitch drives

s = 0

and

\overset{s}{ˉ} = 0

(both low) at once?

With

s = 0

the NMOS is off, but with

\overset{s}{ˉ} = 0

the PMOS gate is low, which turns the PMOS ON. So the gate is not floating — it half-conducts through the PMOS only, passing a degraded (weak-0-style) signal. The genuinely-OFF combination requires

\overset{s}{ˉ} = 1

, so this skew corrupts the intended isolation.

If instead a glitch drives

s = 1

and

\overset{s}{ˉ} = 1

(both high), what happens?

NMOS on (

s = 1

) but PMOS off (gate high), so the gate half-conducts through the NMOS only — a single-transistor weak-1 pass. Neither both-equal glitch floats the node; each leaves exactly one device conducting, breaking the full-rail guarantee.

R_{n}

and

R_{p}

are equal at mid-rail, is

R_{T G}

half of one device's resistance?

Yes. For

R_{n} = R_{p} = R

, the parallel value

R_{T G} = R /2

— the general parallel formula collapses to exactly half when the two are equal.

Connections

Transmission gates — the parent note this bank drills.
Pass transistor logic — the weak-1/weak-0 single-transistor case behind most traps here.
MOSFET threshold voltage — origin of every threshold-drop question.
CMOS inverter — generates $\overset{s}{ˉ}$ and restores levels after TG chains.
Multiplexers and Latches and flip-flops — where the floating/full-rail edge cases matter.
RC delay in interconnects — why "no delay in a chain" is a trap.