This page assumes you have seen none of the notation in the parent note. We will earn every symbol before we use it. By the end you will read each inequality in the parent note — like the condition that turns a transistor on — as an ordinary sentence.
Look at the figure: two tanks. The left is full (high voltage), the right is empty (low voltage). Open a pipe and water flows left→right until the heights match. That "wanting to equalise" is the whole reason current flows. We will keep re-using this height picture.
Why we need this: the entire topic is about whether a signal reaches the full ceiling or full floor, or stops short. Without naming the ceiling and floor, "weak 1" has no meaning.
In the figure the gate is drawn as a little bar sitting near but not touching the channel. Put the right voltage on the gate and the pipe (channel) between source and drain opens; wrong voltage and it stays shut.
Why we need sˉ: the two transistors in a TG turn on with opposite gate voltages, so one gets s and the other gets sˉ. You'll build sˉ physically with a CMOS inverter.
The figure shows both. Notice the little bubble on the PMOS gate — that bubble is the universal drawing symbol for "active LOW", i.e. "this turns on when the gate is 0".
This is the single most important symbol in the whole topic.
Why the topic can't live without Vtn: as an NMOS charges its output up, the source voltage climbs, so VGS=Vgate−Vsourceshrinks. The instant it shrinks down to Vtn, the pipe slams shut. That is why the NMOS output stops at VDD−Vtn instead of the full ceiling — the famous weak 1. Everything the parent derives comes straight from this one inequality.
Why we need this: an ON transmission gate is literally the NMOS pipe (resistance Rn) and PMOS pipe (resistance Rp) side by side between the same two nodes — a parallel pair. That formula is how fast the switch is.
Read it top-down: voltage-as-height gives you rails and VGS; the transistor gives you source/drain; together they define the threshold; the threshold creates weak outputs; the NMOS/PMOS mirror pair plus complementary gates fix the weakness — and that fixed switch is the transmission gate.