Transmission gates: Visual walkthrough — Hardware deep dive

Step 0 — The words we are allowed to use

Before any symbol, plain meaning. A voltage is just how hard electricity is pushed at a point, measured in volts (V). We will use two special voltages:

We will need one more idea, and only one, from MOSFET threshold voltage:

Keep that picture: gate must beat source by $V_{t n}$ , or nothing flows. Everything below is that one rule, watched carefully as things move.

Step 1 — Name the three terminals of a pass transistor

WHAT. Draw one NMOS being used as a switch. Its three current/control wires: the gate (control, driven to $V_{D D}$ to turn it on), and two identical current wires we'll call node A and node B (the body sits underneath, tied to $0$ V as promised in Step 0).

WHY. The whole surprise is coming from a subtlety: for a MOSFET the source is not a fixed wire — it is defined as whichever current wire sits at the lower voltage. We must fix names now so we can watch which wire becomes the source later.

PICTURE. In the figure, gate is the blue wire held at $V_{D D}$ . Node A (left, orange) is where we push a signal in; node B (right, green) is the load we are charging.

Step 2 — Push a logic 1 in and watch node B climb

WHAT. Set gate $= V_{D D}$ (switch ON) and drive node A $= V_{D D}$ (a logic 1). Node B starts empty at $0$ V and begins charging up toward $V_{D D}$ .

WHY. We want to know: does B ever reach the full top rail? To answer, we track the two competing voltages — the gate (frozen at $V_{D D}$ ) and the source.

PICTURE. As B fills, B is the lower wire, so node B is the source. The green level rises; the blue gate stays flat. Watch the shrinking gap between them.

The gate-to-source margin at any instant is: $V_{GS} = gate, frozen V_{D D} - source = node B, rising V_{B}$

The first term never moves (gate is tied to the top rail).
The second term grows as B charges — so the whole margin shrinks as we fill.

Step 3 — The valve throttles itself and stops early

WHAT. Keep filling. The moment $V_{GS}$ shrinks to exactly $V_{t n}$ , the rule from Step 1 says the valve closes. Solve for the B voltage at that instant.

WHY. This is the heart of the "weak 1." The transistor strangles its own current as B rises, because raising B is the very thing that shrinks $V_{GS}$ . No outside villain — it is self-throttling.

PICTURE. The gap between blue (gate) and green (source) has closed to exactly $V_{t n}$ . From here, the green line is stuck: it flattens below the top rail. That flat ceiling is the weak 1.

Set the margin equal to the threshold and read off B: $V_{D D} - V_{B, m a x} = V_{t n} ⟹ V_{B, m a x} = V_{D D} - V_{t n}$

Left side: the margin at the shut-off instant.
Set it to $V_{t n}$ because that is when the valve dies.
Rearranged: node B lands a full $V_{t n}$ short of the top rail. This is the weak 1.

Step 4 — The mirror image: PMOS and the weak 0

First, define the PMOS's threshold, mirroring $V_{t n}$ :

WHAT. Now the other transistor. A PMOS opens when its source beats its gate by the margin $∣ V_{tp} ∣$ . Its source is the higher wire. Drive its gate to $0$ V and try to pass a logic 0 (pull B down toward ground).

WHY. We need the PMOS's weakness too, because the transmission gate is a team. By symmetry we expect the PMOS to fail at the bottom, exactly where the NMOS was strong.

PICTURE. B falls from $V_{D D}$ toward $0$ . B is now the higher side at first, so B is the PMOS source. The orange source-level drops until the gap between it and the grounded gate shrinks to $∣ V_{tp} ∣$ .

$source, falling V_{B} - gate, grounded 0 = ∣ V_{tp} ∣ ⟹ V_{B, m i n} = ∣ V_{tp} ∣$

Source beats gate by $∣ V_{tp} ∣$ at shut-off.
B is stuck a full $∣ V_{tp} ∣$ above ground. This is the weak 0.

So the two transistors fail at opposite rails: NMOS can't reach the top, PMOS can't reach the bottom.

Step 5 — Put them in parallel: each covers the other's weak end

First, name the control wire we are about to use:

WHAT. Wire the NMOS and PMOS between the same A and B. Drive the NMOS gate with $s$ and the PMOS gate with $\overset{s}{ˉ}$ so both are ON together (when $s = 1$ : NMOS gate $= V_{D D}$ , PMOS gate $= 0$ ). This is the transmission gate.

WHY. Pass a 1: near the top rail the NMOS has quit (Step 3), but the PMOS is strong at the top (Step 4 showed it only fails at the bottom). Pass a 0: near the bottom the PMOS has quit, but the NMOS is strong at the bottom. Whichever value you send, at least one valve is still open.

PICTURE. Two valves side by side. Overlay the NMOS "reach" (0 up to $V_{D D} - V_{t n}$ ) and the PMOS "reach" ( $∣ V_{tp} ∣$ up to $V_{D D}$ ). Their coverage overlaps in the middle and together spans the full rail — no gap anywhere.

Step 6 — Why the ON resistance stays flat (bonus: the good news)

First, define the two resistances:

WHAT. ON, each transistor looks like a resistor between A and B; in parallel their combined resistance is $R_{T G} = R_{n} ∥ R_{p} = \frac{R _{n} R _{p}}{R _{n} + R _{p}} .$

WHY $R_{n}$ rises and $R_{p}$ falls with the passed voltage. For the NMOS with its gate frozen at $V_{D D}$ , as node B climbs its source $V_{B}$ rises, so $V_{GS} = V_{D D} - V_{B}$ shrinks toward $V_{t n}$ — the overdrive collapses, the channel pinches, and $R_{n}$ rises (blowing up right at the weak-1 ceiling where the channel vanishes). The PMOS is the mirror: near the top rail its overdrive is largest, so $R_{p}$ is smallest there — $R_{p}$ falls as the passed voltage rises. They weaken at opposite ends.

Consequence. A parallel pair is dominated by the smaller resistor, so as the signal sweeps 0→ $V_{D D}$ the strong one always dominates — the combination stays low and flat.

PICTURE. Plot $R_{n}$ (rising) and $R_{p}$ (falling) versus the passed voltage; their parallel combination is the flat lower curve — roughly voltage-independent. Flat + low = fast charging (see RC delay in interconnects).

$R_{T G} = \frac{R _{n} R _{p}}{R _{n} + R _{p}} \leq min (R_{n}, R_{p})$

Numerator ::: product of the two resistances.
Denominator ::: their sum — makes the result smaller than either alone.
So the TG is never worse than the better of its two transistors, at any voltage.

Step 7 — Degenerate & edge cases (so nothing surprises you)

The one-picture summary

One graph: passed-through voltage on the horizontal axis, the reachable output on the vertical.

The NMOS curve saturates at $V_{D D} - V_{t n}$ (misses the top).
The PMOS curve floors at $∣ V_{tp} ∣$ (misses the bottom).
The TG (their union) is the perfect diagonal — reaches every level from $0$ to $V_{D D}$ .

Recall Feynman retelling — the whole walkthrough in plain words

A transistor-switch has a secret rule: the control wire (gate) only lets current flow while it out-pushes whichever end is lower — the "source" — by a fixed margin. When we fill an empty tank (node B) through an NMOS, the tank level is the source, so filling raises the source, which shrinks the gate's lead, until the lead runs out exactly $V_{t n}$ below full. The tank stops short — a weak 1. The PMOS is the mirror: it empties beautifully but stops $∣ V_{tp} ∣$ short of dead-empty — a weak 0. They fail at opposite ends. So we bolt them side by side, controlled by opposite signals ( $s$ and $\overset{s}{ˉ}$ ) so both are open at once: filling? the ceiling-lover (PMOS) finishes it; emptying? the floor-lover (NMOS) finishes it. Now the tank always goes fully full and fully empty — a near-perfect switch. Bonus: because the weak one is always paired with a strong one, the combined "pipe resistance" stays low and flat across the whole range, so it's fast too.

Recall

Where does the weak-1 ceiling sit? ::: At $V_{D D} - V_{t n}$ — the NMOS shuts when its rising source is $V_{t n}$ below the gate. Where does the weak-0 floor sit? ::: At $∣ V_{tp} ∣$ — the PMOS shuts when its falling source is $∣ V_{tp} ∣$ above its grounded gate. In a TG, who reaches the top rail and who reaches the bottom? ::: PMOS reaches the top (strong 1); NMOS reaches the bottom (strong 0). Why is $R_{T G}$ roughly flat vs voltage? ::: The two transistors are strong at opposite rails; the parallel pair follows the smaller resistance, so it never spikes. What are $s$ and $\overset{s}{ˉ}$ ? ::: $s$ is the single control/select input; $\overset{s}{ˉ}$ is its complement — NMOS gate gets $s$ , PMOS gate gets $\overset{s}{ˉ}$ .

Connections

3.2.09 Transmission gates (Hinglish) — the parent topic (Hinglish master note).
Pass transistor logic — the single-transistor case whose weak 1 / weak 0 we derived here.
MOSFET threshold voltage — the source of $V_{t n}$ and $V_{tp}$ (and the body effect we chose to ignore).
CMOS inverter — generates the complement $\overset{s}{ˉ}$ and restores levels after TG chains.
Multiplexers and Latches and flip-flops — where these full-rail switches get used.
RC delay in interconnects — why the flat, low $R_{T G}$ of Step 6 matters for speed.