Transmission gates — Hinglish notes

3.2.9 · Hardware › CMOS Circuit Design

Transmission gate KYA hai?

Hume do transistors ki ZAROORAT kyun hai? (Threshold-drop ki kahani)

TG ka poora reason ek single MOS pass transistor ka defect hai. Chaliye isse derive karte hain.

NMOS ki "weak 1" ko derive karna

Gate ko $V_{D D}$ ( $s = 1$ ) par drive kiya gaya hai. Hum ek logic 1 ( $V_{D D}$ ) node A mein push karte hain aur node B ko rise hote dekhte hain.

Node B $0$ se $V_{D D}$ ki taraf rise karta hai.
NMOS ke liye, source node B hai (jab woh charge ho raha hai tab low side).
Transistor on rehta hai jab $V_{GS} = V_{D D} - V_{B} > V_{t n}$ .
Yeh shut off ho jaata hai jis pal $V_{B} = V_{D D} - V_{t n}$ ho jaata hai.

$V_{B, m a x}^{N M O S} = V_{D D} - V_{t n}$

Yeh step kyun? Kyunki jaise hi $V_{GS}$ exactly $V_{t n}$ tak girta hai, koi drive nahi bachti — channel gayab ho jaata hai, isliye B kabhi full rail tak nahi pahunch sakta. Yahi weak 1 hai.

PMOS ki "weak 0" ko derive karna

Ek PMOS tab turn on hota hai jab $V_{GS} < V_{tp}$ (jahan $V_{tp} < 0$ ), yaani $V_{S G} > ∣ V_{tp} ∣$ . Iska "source" high terminal hota hai. Agar tum ek 0 ko PMOS se pass karne ki koshish karo, output sirf tab tak girta hai jab tak:

$V_{B, m i n}^{P M O S} = ∣ V_{tp} ∣$

Yeh step kyun? Wohi self-throttling: jaise B girta hai, PMOS ka $V_{S G}$ ghatta hai; yeh $∣ V_{tp} ∣$ par mar jaata hai. Yahi weak 0 hai.

Formula Pass strengths ka summary

Pass through	Strong output	Weak output
Sirf NMOS	$0$ ( $0$ V tak)	$1$ (sirf $V_{D D} - V_{t n}$ tak)
Sirf PMOS	$1$ ( $V_{D D}$ tak)	$0$ (sirf $
Dono parallel mein (TG)	$0$ aur $1$	— koi nahi —

Dono ko saath rakho: jab 1 pass karte ho, PMOS use full rail tak le jaata hai; jab 0 pass karte ho, NMOS use ground tak le jaata hai. Chahe koi bhi value ho, kam se kam ek transistor strong hota hai. Yahi transmission gate ka poora justification hai.

Yeh electrically kaisa behave karta hai (resistance)

KAHAN use hota hai

Multiplexers: do TGs, complementary select → saaf 2:1 MUX bina threshold loss ke.
Latches / flip-flops: TG feedback loop mein state hold ya update karne ke liye.
XOR / XNOR gates: bahut compact TG-based implementations.
Analog switches / sample-and-hold: bidirectional, low-distortion signal pass.

Worked examples

Common mistakes (Steel-man + fix)

Active recall

Recall Reveal karne se pehle jawab do

NMOS strong 1 kyun pass nahi kar sakta?
$V_{D D}$ pass karte waqt ek NMOS pass-transistor output kis voltage par settle hota hai?
Ek TG ke do gates ko kaun se signals drive karte hain?
TG ki ON resistance roughly voltage-independent kyun hai?

Jawab: 1) Yeh self-shut ho jaata hai jab $V_{GS} = V_{t n}$ , isliye output $V_{D D} - V_{t n}$ par ruk jaata hai. 2) $V_{D D} - V_{t n}$ . 3) $s$ NMOS ko, $\overset{s}{ˉ}$ PMOS ko (complementary). 4) NMOS top rail ke paas aur PMOS bottom rail ke paas kamzor hote hain; parallel combination roughly flat rehta hai.

Recall Feynman: 12-saal ke bachche ko samjhao

Socho ek paani ka pipe valve ke saath. Ek tarah ka valve (NMOS) paani bahut accha drain kar sakta hai, lekin jab tum tank fill karne ki koshish karo toh yeh top se thoda pehle ruk jaata hai. Doosra valve (PMOS) bilkul top tak fill karta hai lekin last bit empty nahi kar sakta. Toh hum dono valves ko side by side rakh dete hain aur unhe saath use karte hain: jab bhi fill karo, accha-filler kaam karta hai; jab bhi empty karo, accha-emptier kaam karta hai. Ab tank hamesha poora full aur poora empty jaata hai. Yahi transmission gate hai — electricity ke liye ek smart double valve.

Connections

Pass transistor logic — single-transistor case jiska weakness TG theek karta hai.
MOSFET threshold voltage — $V_{t n}$ / $∣ V_{tp} ∣$ drops ka source.
CMOS inverter — $\overset{s}{ˉ}$ generate karne aur TG chains ke baad signals restore karne ke liye use hota hai.
Multiplexers aur Latches and flip-flops — canonical TG applications.
RC delay in interconnects — kyun lambi TG chains ko buffering chahiye.

NMOS sirf weak 1 kyun pass karta hai?

Yeh self-cut off ho jaata hai jab

V_{GS} = V_{t n}

; kyunki uska source (output) rise karta hai, output

V_{D D} - V_{t n}

par ruk jaata hai.

Ek NMOS pass transistor

V_{D D}

pass karte waqt zyada se zyada kitna voltage deliver karta hai?

V_{D D} - V_{t n}

Ek PMOS pass transistor 0 pass karte waqt kam se kam kitna voltage deliver karta hai?

∣ V_{tp} ∣

Transmission gate kya hota hai?

Ek NMOS aur PMOS parallel mein complementary gate signals ke saath, ek near-ideal bidirectional switch banate hue.

Ek TG ko kaun se gate signals drive karte hain?

s

NMOS gate ko aur

\overset{s}{ˉ}

PMOS gate ko (complementary).

TG se strong 1 kaun sa transistor carry karta hai?

PMOS.

TG se strong 0 kaun sa transistor carry karta hai?

NMOS.

TG ON resistance ka formula?

R_{T G} = R_{n} ∥ R_{p} = \frac{R _{n} R _{p}}{R _{n} + R _{p}}

TG resistance roughly voltage-independent kyun hai?

NMOS top rail ke paas aur PMOS bottom rail ke paas kamzor hote hain; parallel combination roughly flat rehta hai.

Kya transmission gate directional hota hai?

Nahi, yeh bidirectional hai aur signals restore/amplify nahi karta.

TG gates wiring mein common mistake kya hai?

Dono ko same signal se drive karna; PMOS ko

\overset{s}{ˉ}

chahiye, warna ek transistor hamesha off rehta hai.

Ek TG application?

2:1 multiplexer (saath hi latches, XOR gates, analog switches bhi).