Fan-in and fan-out limits — Hinglish notes

3.2.8 · Hardware › CMOS Circuit Design

HUM KISI BAARE MEIN BAAT KAR RAHE HAIN?

LIMITS KYUN HOTE HAIN? (first principles)

Ek CMOS output switch karta hai ek load capacitance $C_{L}$ ko ek transistor ke through charge karke jo ek resistor ki tarah act karta hai $R$ . Delay RC time constant se set hoti hai.

Fan-out delay scratch se derive karna

Step 1 — switching ko model karo. Jab output $h$ identical gate loads drive karta hai, toh total load capacitance hoti hai: $C_{L} = h C_{g} + C_{p a r}$ Ye step kyun? Har downstream input essentially ek capacitor $C_{g}$ hai; $h$ unke parallel mein add hote hain, plus driver ki apni self/parasitic capacitance $C_{p a r}$ .

Step 2 — delay ko RC ki tarah likho. Is cap ko charge karne wale transistor ki on-resistance $R$ hai. Propagation delay RC product ke proportional hai: $t_{p d} = 0.69 R C_{L}$ Ye step kyun? $V (t) = V_{D D} (1 - e^{- t / R C})$ ko 50% point ke liye solve karne par $t = R C ln 2 = 0.69 R C$ milta hai. Wahan se "0.69" aata hai — ye derived hai, magic nahi.

Step 3 — normalize karo (logical effort form). Electrical effort (a.k.a. fan-out) define karo: $f = \frac{C _{L}}{C _{in}}$ Tab delay (normalized units mein) hoti hai: $d = g \cdot f + p$ jahan $g$ = logical effort (gate inverter se kitna worse hai), $f$ = electrical effort (fan-out), $p$ = parasitic delay.

Fan-in kyun hurt karta hai — derive karna

Step 1 — series resistance add hoti hai. $N$ NMOS transistors series mein rakho (ek NAND- $N$ ). Series mein resistances add hoti hain: $R_{s t a c k} = N R$ Ye step kyun? Ohmic series resistances sum hoti hain. Pull-down path ab $N$ times zyada resistive hai.

Step 2 — compensate karne ke liye sizing. Resistance constant rakhne ke liye har transistor ko $N$ se widen karo → lekin wider transistors ka input capacitance $N \times$ bada hota hai. Toh har input load badhta hai, pichle stage ka fan-out raise hota hai.

Step 3 — parasitic capacitance badhti hai. Stacked transistors ke beech internal source/drain junctions har ek capacitance add karte hain. Parasitic delay roughly scale hoti hai: $p_{N A N D - N} \approx N p_{in v}$

NOR kyun worse hai: "2N" PMOS (mobility ~2× worse) stack karne se aata hai, toh wider PMOS = per unit drive zyada capacitance.

Worked Examples

Common Mistakes

Flashcards

Static CMOS gate ka fan-in kya hota hai?

Inputs ki sankhya = pull-up ya pull-down network mein series transistors ki sankhya.

Fan-out kya hota hai?

Gate-input loads ki sankhya jo ek single output ko drive karni padti hai (total load capacitance / ek input cap).

Fan-out delay kyun badhata hai?

Har load capacitance

C_{g}

add karta hai; delay

= 0.69 R C_{L}

load ke saath linearly badhti hai, toh

d = g f + p

with

f = C_{o u t} / C_{in}

RC delay mein 0.69 kahan se aata hai?

V = V_{D D} (1 - e^{- t / R C})

ka 50% point solve karne par

t = R C ln 2 = 0.69 R C

milta hai.

NAND-

N

gate ka Logical effort?

g = (N + 2) /3

NOR-

N

gate ka Logical effort?

g = (2 N + 1) /3

High fan-in ke liye NOR, NAND se worse kyun hai?

NOR weak PMOS series mein stack karta hai; PMOS mobility ~2× kam hai toh uska logical effort ~2× faster badhta hai.

Parasitic delay fan-in

N

ke saath kaise scale hoti hai?

Roughly

p \approx N p_{in v}

internal junction caps add hone ki wajah se.

High-fan-in gate ka fix?

Low-fan-in gates ke balanced tree mein split karo.

High-fan-out net ka fix?

Buffers insert karo / driver ko upsize karo (ya buffer tree), area/prior-stage load trade karke speed ke liye.

Logical-effort form mein delay equation?

d = g f + p

, jahan

g

=logical effort,

f

=electrical effort (fan-out),

p

=parasitic delay.

Pure CMOS mein fan-out ko kya limit karta hai — current ya capacitance?

Capacitance (speed); gate leakage ~0 hai toh DC current limit negligible hai.

Recall Feynman: 12-year-old ko explain karo

Socho ek baccha (gate) cups (loads) mein paani daal raha hai. 2 cups mein daale toh jaldi; 10 cups mein daale toh bahut time lagta hai — ye fan-out hai. Ab socho ek line of bacche ek dusre ko bucket pass kar rahe hain paani end tak pahunchne se pehle — lambi line slow hoti hai, ye fan-in hai (kai transistors ek row mein). Fast jaane ke liye: ek bacche ko 20 cups mat bharo, aur 8 bacho ki line mat banao. Chhoti lines aur bahut saare helpers use karo (small gates, buffers).

Connections

CMOS Static Logic Gates — NAND/NOR pull-up/pull-down nets kaise bante hain.
Logical Effort — $d = g f + p$ framework jo yahan use kiya gaya hai.
RC Delay Model — $0.69 R C$ ka origin.
Buffer Sizing and Inverter Chains — bade fan-out ko fix karna.
Propagation Delay and Timing — jahan ye limits clock speed set karti hain.
Transistor Sizing — series resistance se ladne ke liye widening.