Propagation delay and rise - fall times — Hinglish notes

3.2.7 · Hardware › CMOS Circuit Design

1. Hum kya measure kar rahe hain?

DO ALAG POINTS (50% vs 10/90%) KYUN?

Delay mein 50% use hota hai kyunki yeh logic decision point hai — jahan agle gate ke liye "1" "0" ban jaata hai.
Rise/fall mein 10–90% use hota hai kyunki signals rails ke paas slowly asymptote karte hain; 0%→100% time infinite hoga (exponential kabhi truly rail tak nahi pahunchta), isliye hum ends clip karte hain.

Figure — Propagation delay and rise - fall times

2. First principles se delay derive karna

KYA HO RAHA HAI: output ko fall karaane ke liye, NMOS charge $C_{L}$ se ground mein khiinchta hai.

Governing equation (output node pe charge conservation): $C_{L} \frac{d V _{o u t}}{d t} = - i_{D N} (t)$

Pura khel yeh hai: discharge current $i_{D N}$ ke liye hum kaun sa model use karte hain? Do useful models hain:

Model A — RC (transistor as a resistor)

Jab drain–source voltage chhota hota hai toh transistor ek resistor $R_{e q}$ ki tarah behave karta hai. Tab yeh sirf ek RC discharge hai: $C_{L} \frac{d V}{d t} = - \frac{V}{R _{e q}} \Rightarrow V (t) = V_{D D} e^{- t / (R_{e q} C_{L})}$

$t_{p H L}$ derive karo — $V = V_{D D} /2$ set karo: $\frac{V _{D D}}{2} = V_{D D} e^{- t_{p H L} / (R_{e q} C_{L})} \Rightarrow e^{- t_{p H L} / τ} = \frac{1}{2}$ $t_{p H L} = R_{e q} C_{L} ln 2 \approx 0.69 R_{e q} C_{L}$ $ln 2$ kyun? Kyunki hum half-way point cross karte hain, aur $- ln (1/2) = ln 2$ .

$t_{f}$ derive karo (10%→90%) usi exponential ke liye: $t_{f} = τ ln \frac{0.9 V _{D D}}{0.1 V _{D D}} = R_{e q} C_{L} ln 9 \approx 2.2 R_{e q} C_{L}$ $ln 9$ kyun? $0.9 V_{D D}$ se $0.1 V_{D D}$ tak jaane ka time hai $τ [ln (V_{D D} /0.1 V_{D D}) - ln (V_{D D} /0.9 V_{D D})] = τ ln 9$ .

Model B — Saturation-current (constant-current) model

Switch ke shuruaat mein, $V_{D S}$ bada hota hai isliye transistor saturated hota hai aur roughly constant current $I_{D S A T}$ deliver karta hai. Tab: $C_{L} \frac{d V}{d t} = - I_{D S A T} = const \Rightarrow V (t) = V_{D D} - \frac{I _{D S A T}}{C _{L}} t$ $V_{D D} /2$ drop karne ka time: $t_{p H L} = \frac{C _{L} V _{D D} /2}{I _{D S A T}} = \frac{C _{L} V _{D D}}{2 I _{D S A T}}$

3. $R_{e q}$ ≈ (kuch / current) kyun hota hai?

Equivalent resistance actually poore swing pe true $V / I$ ratio ka ek average hai. Ek standard estimate transition ke dono ends pe current use karta hai. Ek common closed form: $R_{e q} \approx \frac{3}{4} \frac{V _{D D}}{I _{D S A T}} (1 - \frac{7}{9} λ V_{D D})$ Jo baat yaad rakhni hai woh yeh hai: $R_{e q}$ scales as $1/ (W / L)$ — width double karo, resistance half hogi, delay half hogi (tab tak jab tak tum jo load drive karte ho woh bhi double na ho jaye).

4. Worked examples

5. Common mistakes (steel-manned)

6. Feynman + memory aids

Recall Ek 12-saal ke bachche ko samjhao

Socho tum ek bucket (capacitor) ko ek hose (transistor) se bhar rahe ho. Badi bucket bhar ne mein zyada time lagti hai; moti hose jaldi bharti hai. Propagation delay hai "kitna time laga bucket half bhar ne mein" — tabhi tumhara dost downstream decide karta hai ki light on hui. Rise time hai "almost-empty (10%) se almost-full (90%) mein kitna time laga" — pour kitni sharp dikhti hai. Kabhi exactly 100% full hone ka wait mat karo, kyunki last kuch drops hamesha slowly trickle karte rehte hain.

7. Flashcards

Ek gate mein koi bhi delay kyun hoti hai?

Ek finite drive current output load capacitance

C_{L}

ko charge/discharge karta hai;

C d V / d t = i

ko nonzero time lagta hai.

Propagation delay

t_{p H L}

ki definition?

Input ke 50%

V_{D D}

cross karne se output ke 50% cross karne tak ka time, jab output High→Low jaa raha ho.

Delay 50% pe kyun measure hoti hai?

Yeh logic threshold hai jahan agla gate apna decision flip karta hai.

Rise/fall 10–90% pe kyun measure hote hain, 0–100% pe kyun nahi?

Exponential output rail ke paas asymptotically approach karta hai, isliye 0–100% time infinite hoga; 10–90% slow tails ko clip karta hai.

RC-model formula

t_{p H L}

ke liye?

t_{p H L} = 0.69 R_{e q} C_{L} = R_{e q} C_{L} ln 2

ln 2

kahan se aata hai?

50% crossing pe

e^{- t / τ} = 1/2

set karne se.

RC-model formula fall time ke liye?

t_{f} = 2.2 R_{e q} C_{L} = R_{e q} C_{L} ln 9

(10%→90%).

t_{p H L}

ke liye constant-current model?

t_{p H L} = C_{L} V_{D D} / (2 I_{D S A T})

; sirf half swing matter karta hai.

Pure exponential ke liye fixed ratio

t_{f} / t_{p H L}

ln 9/ ln 2 \approx 3.17

R_{e q}

transistor width

W

ke saath kaise scale karta hai?

R_{e q} \propto 1/ W

; wider transistor = lower resistance = faster.

Matched inverter mein PMOS ko ~2× NMOS width kyun banate hain?

PMOS mobility ~½ of NMOS;

W_{p}

double karne se

R_{e q p} = R_{e q n}

equal hoti hai isliye

t_{r} = t_{f}

Dono se overall gate delay?

t_{p} = \frac{1}{2} (t_{p H L} + t_{p L H})

Connections

CMOS Inverter DC Transfer Characteristic — $V_{50%}$ / switching threshold kahan se aata hai.
Equivalent Resistance of MOSFET — $R_{e q}$ ka origin.
Load Capacitance Estimation — $C_{L}$ compute karna (wire + fan-out).
Logical Effort and Fan-out-of-4 — optimal sizing/buffering.
Dynamic Power Dissipation — same $C_{L} V_{D D}$ charge, alag consequence (energy).
Elmore Delay — RC delay ko multi-node RC trees tak extend karna.