Noise margins (NMH, NML): Worked examples — Hardware deep dive

This page is the exhaustive drill room for noise margins. The parent note built the four voltages and the two formulas. Here we run them through every kind of input a problem can hand you — normal numbers, zeros, degenerate (broken) gates, limiting values, a word problem, and an exam trap.

Everything on this page uses only these two facts, so keep them in view:

The scenario matrix

Every noise-margin problem falls into one of these cells. The examples below are labelled with the cell they cover, and together they hit all of them.

Cell	What makes it special	Covered by
C1 — balanced positive	both margins comfortably $> 0$ , symmetric	Ex 1
C2 — unbalanced positive	one margin much smaller (skewed gate)	Ex 2
C3 — zero margin	a margin lands exactly at $0$ (boundary of failure)	Ex 3
C4 — negative margin	levels overlap → gate broken even with no noise	Ex 4
C5 — degenerate VTC	$V_{O H} = V_{O L}$ or no valid levels (dead gate)	Ex 5
C6 — limiting behaviour	$V_{D D} \to 0$ scaling; margin trend	Ex 6
C7 — real-world word problem	given noise amplitude, will it flip?	Ex 7
C8 — exam twist	mismatched driver/receiver families, chained	Ex 8

The picture below is our map. Read it top to bottom as a single voltage axis (volts, running $0$ at the bottom to $3.7$ at the top):

the green line is $V_{O H} = 3.3 V$ (a driver's guaranteed HIGH),
the blue line is $V_{I H} = 2.0 V$ (the receiver's HIGH floor),
the orange line is $V_{I L} = 0.8 V$ (the receiver's LOW ceiling),
the gray line is $V_{O L} = 0.2 V$ (a driver's guaranteed LOW).

The blue double-headed arrow on the left spans green-down-to-blue: that height is $N M_{H}$ . The orange double-headed arrow spans gray-up-to-orange: that height is $N M_{L}$ . The pale blue band at the top is "valid 1", the pale orange band at the bottom is "valid 0", and the gray band between $V_{I L}$ and $V_{I H}$ is the forbidden region. Every example refers back to these arrows.

Figure s01 — The voltage map. Green = $V_{O H}$ , blue = $V_{I H}$ , orange = $V_{I L}$ , gray = $V_{O L}$ . Blue arrow (left) = $N M_{H}$ , orange arrow (middle) = $N M_{L}$ . Pale blue band = valid 1, gray band = forbidden, pale orange band = valid 0.

Ex 1 — Cell C1: balanced, both positive

Worked example

Statement. A gate has $V_{O H} = 3.3 V$ , $V_{O L} = 0.2 V$ , $V_{I H} = 2.0 V$ , $V_{I L} = 0.8 V$ . Find both margins and the robustness.

Forecast. The high side starts at $3.3 V$ and only needs $2.0 V$ — a wide $1.3 V$ -ish gap. The low side starts at $0.2 V$ and may rise only to $0.8 V$ — a narrower gap, maybe $0.6 V$ . Guess: the low side is the tighter one. Which will set the robustness?

Step 1 — $N M_{H} = V_{O H} - V_{I H} = 3.3 V - 2.0 V = 1.3 V$ . Why this step? A HIGH signal starts at the guaranteed ceiling $V_{O H}$ ; noise can only pull it down toward the receiver's floor $V_{I H}$ . The gap $3.3 - 2.0$ is how far it may fall before failure. In figure s01 this is the blue double-headed arrow reaching from the green $V_{O H}$ line down to the blue $V_{I H}$ line.

Step 2 — $N M_{L} = V_{I L} - V_{O L} = 0.8 V - 0.2 V = 0.6 V$ . Why this step? A LOW signal starts at the floor $V_{O L} = 0.2 V$ ; noise pushes it up toward the receiver's ceiling $V_{I L} = 0.8 V$ . The gap is the tolerable rise — in figure s01 this is the orange double-headed arrow from the gray $V_{O L}$ line up to the orange $V_{I L}$ line. Note the subtraction order: the larger number ( $V_{I L}$ ) comes first so the answer is positive.

Step 3 — Robustness $= min (1.3 V, 0.6 V) = 0.6 V$ . Why this step? A chain is only as strong as its weakest link; the LOW side is the vulnerable one here (its orange arrow in figure s01 is visibly shorter than the blue one), exactly as forecast.

Verify. Both positive ✓. There is also a neat cross-check. Add the two margins and expand each bracket: $N M_{H} + N M_{L} = (V_{O H} - V_{I H}) + (V_{I L} - V_{O L}) = V_{O H} - V_{I H} + V_{I L} - V_{O L} .$ Now reorder the four terms so the two output levels sit together and the two input levels sit together: $= (V_{O H} - V_{O L}) + (V_{I L} - V_{I H}) = (V_{O H} - V_{O L}) - (V_{I H} - V_{I L}) .$ (The last step just factors a minus sign out of $V_{I L} - V_{I H}$ .) In words: (total output swing) minus (width of the forbidden band). Plug numbers: output swing $= 3.3 - 0.2 = 3.1 V$ ; forbidden band $= 2.0 - 0.8 = 1.2 V$ ; difference $= 1.9 V$ . And directly $N M_{H} + N M_{L} = 1.3 + 0.6 = 1.9 V$ ✓. Same number two ways → our arithmetic is sound. Units are volts throughout ✓.

Ex 2 — Cell C2: unbalanced (skewed gate)

Worked example

Statement. A CMOS inverter with weakened PMOS (see Static Gain and Regenerative Property for how skew moves the threshold) has rail-to-rail output $V_{O H} = 1.8 V$ , $V_{O L} = 0 V$ , but its switching point shifted down, giving $V_{I L} = 0.45 V$ , $V_{I H} = 0.65 V$ . Compute margins.

Forecast. Lowering the threshold pulls both $V_{I L}$ and $V_{I H}$ down. $N M_{H} = V_{O H} - V_{I H}$ subtracts a smaller $V_{I H}$ → grows. $N M_{L} = V_{I L} - V_{O L}$ has a smaller ceiling → shrinks. Guess: high margin big, low margin small.

Step 1 — $N M_{H} = 1.8 V - 0.65 V = 1.15 V$ . Why? Rail top minus the (now lower) receiver floor → a wide cushion.

Step 2 — $N M_{L} = 0.45 V - 0 V = 0.45 V$ . Why? The receiver ceiling dropped to $0.45 V$ while the driver still sits at $0 V$ → a thin cushion.

Step 3 — Robustness $= min (1.15 V, 0.45 V) = 0.45 V$ . Why? Skew traded high-side safety for low-side risk; the minimum fell below the balanced case.

Verify. Both positive ✓, so the gate still works — just poorly. Compare to a symmetric gate at the same $V_{D D}$ : threshold at $0.9 V$ gives $N M_{H} = N M_{L} = 0.9 V$ . Here $min = 0.45 V < 0.9 V$ ✓ — skew always lowers the minimum margin. This is the D3 confirmation of the parent's "symmetric design maximises the minimum".

Ex 3 — Cell C3: a margin exactly zero (knife-edge)

Worked example

Statement. $V_{O H} = 2.5 V$ , $V_{I H} = 1.6 V$ , $V_{O L} = 1.1 V$ , $V_{I L} = 1.1 V$ . Find margins. What does $N M_{L} = 0$ mean?

Forecast. $V_{I L}$ and $V_{O L}$ are the same number. What happens when the receiver ceiling equals the driver floor? Guess: zero low-side cushion.

Step 1 — $N M_{H} = 2.5 V - 1.6 V = 0.9 V$ . Why? Ordinary positive high margin.

Step 2 — $N M_{L} = V_{I L} - V_{O L} = 1.1 V - 1.1 V = 0 V$ . Why? The driver's LOW output sits exactly at the highest voltage the receiver still reads as 0. There is no room to spare — the smallest positive noise flips the read. This is the exact boundary of the forbidden region (imagine the orange arrow of figure s01 shrinking to zero length).

Step 3 — Robustness $= min (0.9 V, 0 V) = 0 V$ . Why? A zero-margin gate is technically valid with zero noise but fails with any real noise. In practice it is treated as failed.

Verify. Sign check: $N M_{L} \geq 0$ but not $> 0$ ✓ — sits on the knife-edge. If we nudge $V_{O L}$ up by even $0.01 V$ , $N M_{L}$ goes negative → we cross into Cell C4 next.

Ex 4 — Cell C4: negative margin (broken gate)

Worked example

Statement. $V_{O H} = 2.0 V$ , $V_{I H} = 2.3 V$ , $V_{O L} = 0.5 V$ , $V_{I L} = 0.4 V$ . Are the margins valid?

Forecast. Look carefully: the guaranteed HIGH output $2.0 V$ is below what the receiver needs ( $V_{I H} = 2.3 V$ ). That can't be safe. Guess: negative high margin.

Step 1 — $N M_{H} = 2.0 V - 2.3 V = - 0.3 V$ . Why? The driver's best "1" is $0.3 V$ below the receiver's minimum "1". Even with zero noise the receiver never sees a valid high. Negative margin = overlap into the forbidden region.

Step 2 — $N M_{L} = 0.4 V - 0.5 V = - 0.1 V$ . Why? The driver's "0" ( $0.5 V$ ) is already above the highest voltage the receiver accepts as 0 ( $0.4 V$ ). Broken on both sides.

Step 3 — Robustness $= min (- 0.3 V, - 0.1 V) = - 0.3 V$ . Why? Any negative value means the logic levels overlap the undefined band; the gate can misread without any noise at all.

Verify. Negative results are the machine flag for "invalid design" ✓. This is exactly the parent's "why must both margins be positive" rule made concrete: overlap $\Rightarrow$ failure.

Ex 5 — Cell C5: degenerate VTC (dead gate)

Worked example

Statement. A gate with almost no gain (see the flat-VTC case in Static Gain and Regenerative Property) collapses so that $V_{O H} = V_{O L} = 0.9 V$ , and the unity-gain points merge: $V_{I H} = V_{I L} = 0.9 V$ . What are the margins?

Forecast. If the output never leaves $0.9 V$ , there is no "high" and no "low" — the gate outputs the same thing regardless of input. Guess: both margins zero, and actually meaningless.

Step 1 — $N M_{H} = V_{O H} - V_{I H} = 0.9 V - 0.9 V = 0 V$ . Why? With no output swing, the "high" level equals the switching threshold — zero separation.

Step 2 — $N M_{L} = V_{I L} - V_{O L} = 0.9 V - 0.9 V = 0 V$ . Why? Same collapse on the low side. There is no distinct 0 and 1 to protect.

Step 3 — Interpretation. Why? This is the degenerate limit: gain $∣ A_{v} ∣ \leq 1$ everywhere, so the gate cannot restore levels. Both margins vanish → this is not usable digital logic. The regenerative property ( $∣ A_{v} ∣ > 1$ near $V_{M}$ ) is precisely what stops this collapse.

Verify. $V_{O H} = V_{O L} \Rightarrow N M_{H} + N M_{L} = (V_{O H} - V_{O L}) - (V_{I H} - V_{I L}) = 0 - 0 = 0$ , and each is individually $0 V$ ✓. Degenerate cell confirmed.

Ex 6 — Cell C6: limiting behaviour (supply scaling)

Worked example

Statement. Take an ideal symmetric CMOS inverter where margins track the supply: $N M_{H} = N M_{L} = V_{D D} /2$ (rail-to-rail swing, threshold at $V_{D D} /2$ ; details in Power Supply Scaling). Evaluate at $V_{D D} = 1.8 V, 1.0 V, 0.5 V$ . What happens as $V_{D D} \to 0$ ?

Forecast. Margin is half the supply, so halving $V_{D D}$ halves the margin. As $V_{D D} \to 0$ the margin $\to 0$ . Guess: shrinks linearly to nothing.

Step 1 — $V_{D D} = 1.8 V$ : margin $= 1.8/2 = 0.9 V$ . Why? Baseline strong margin — the classic case.

Step 2 — $V_{D D} = 1.0 V$ : margin $= 1.0/2 = 0.5 V$ . Why? Same formula, smaller supply → smaller absolute cushion.

Step 3 — $V_{D D} = 0.5 V$ : margin $= 0.5/2 = 0.25 V$ . Why? Now only $250 mV$ of noise tolerance — real coupling noise starts to threaten this.

Step 4 — Limit $V_{D D} \to 0$ : margin $\to 0$ . Why? $V_{D D} \to 0 lim \frac{V _{D D}}{2} = 0$ . Below a certain $V_{D D}$ the swing can no longer clear the transistor thresholds and noise immunity disappears. This is the fundamental limit on low-voltage logic.

Verify. In figure s02, margin vs $V_{D D}$ is the straight blue line through the origin with slope $\frac{1}{2}$ . Each computed orange dot ( $1.8, 0.9$ ), ( $1.0, 0.5$ ), ( $0.5, 0.25$ ) lands exactly on that line, and the red dot at the origin marks the $V_{D D} \to 0$ limit ✓.

Figure s02 — Noise margin vs supply voltage. Blue line = ideal margin $V_{D D} /2$ (slope $\frac{1}{2}$ through the origin); orange dots = the three computed cases; red dot at the origin = the $V_{D D} \to 0$ limit where margin vanishes.

Ex 7 — Cell C7: real-world word problem

Worked example

Statement. A driver on a chip guarantees $V_{O H} = 1.62 V$ , $V_{O L} = 0.10 V$ . The receiving gate has $V_{I H} = 1.10 V$ , $V_{I L} = 0.55 V$ . A neighbouring wire couples in noise of peak amplitude $0.40 V$ (it can push either direction). Does the link survive both a stored 1 and a stored 0?

Forecast. Compute both margins, then compare each to the $0.40 V$ noise. Guess: high side survives (big gap), low side... let's see.

Step 1 — $N M_{H} = 1.62 V - 1.10 V = 0.52 V$ . Why? A stored 1 can drop this far before the receiver mis-reads. Since $0.52 V > 0.40 V$ , the noise cannot flip a 1 → HIGH survives.

Step 2 — $N M_{L} = 0.55 V - 0.10 V = 0.45 V$ . Why? A stored 0 can rise this far. Since $0.45 V > 0.40 V$ , noise cannot flip a 0 → LOW survives.

Step 3 — Verdict. Why? The link survives iff noise amplitude $<$ both margins, i.e. $< min (0.52 V, 0.45 V) = 0.45 V$ . Here $0.40 V < 0.45 V$ → safe, but the low side has only $0.05 V$ of headroom to spare.

Verify. Headroom on the tight side: $0.45 V - 0.40 V = 0.05 V > 0$ ✓ safe. If noise grew to $0.50 V$ it would exceed $N M_{L} = 0.45 V$ and the 0 would flip — the design is only marginally safe.

Ex 8 — Cell C8: exam twist (mismatched families, chained)

Worked example

Statement (the trap). Family A drives Family B. Family A outputs: $V_{O H}^{A} = 3.3 V$ , $V_{O L}^{A} = 0.4 V$ . Family B inputs: $V_{I H}^{B} = 2.0 V$ , $V_{I L}^{B} = 0.8 V$ . Then B drives back to A, where A's inputs are $V_{I H}^{A} = 2.4 V$ , $V_{I L}^{A} = 0.9 V$ , and B outputs $V_{O H}^{B} = 2.5 V$ , $V_{O L}^{B} = 0.2 V$ . Find the margins for each direction and the worst margin in the whole loop.

Forecast. The trap is using the wrong gate's input thresholds. Margins always pair this driver's output with the next gate's input. Direction A→B uses B's inputs; direction B→A uses A's inputs. Guess: the B→A high side is tightest because $V_{O H}^{B} = 2.5 V$ is close to $V_{I H}^{A} = 2.4 V$ .

Step 1 — A→B, HIGH: $N M_{H} = V_{O H}^{A} - V_{I H}^{B} = 3.3 V - 2.0 V = 1.3 V$ . Why? A's high output crossing into B's high threshold. Pair A's output with B's input — one gate boundary crossed.

Step 2 — A→B, LOW: $N M_{L} = V_{I L}^{B} - V_{O L}^{A} = 0.8 V - 0.4 V = 0.4 V$ . Why? B's low ceiling minus A's low floor. Larger number ( $V_{I L}^{B}$ ) first so the result is positive.

Step 3 — B→A, HIGH: $N M_{H} = V_{O H}^{B} - V_{I H}^{A} = 2.5 V - 2.4 V = 0.1 V$ . Why? B's weaker high ( $2.5 V$ ) barely clears A's demanding threshold ( $2.4 V$ ) → a razor-thin $0.1 V$ . This is the exam's hidden weak link — exactly as forecast.

Step 4 — B→A, LOW: $N M_{L} = V_{I L}^{A} - V_{O L}^{B} = 0.9 V - 0.2 V = 0.7 V$ . Why? A's low ceiling minus B's low floor — comfortable.

Step 5 — Worst margin in the loop $= min (1.3, 0.4, 0.1, 0.7) V = 0.1 V$ . Why? The loop is only as robust as its most fragile hop — the B→A high transition. Mismatched families (relevant to Fan-out and Loading too) can silently create a near-failing edge.

Verify. All four margins are positive ✓, so the loop technically works, but $0.1 V$ is dangerously small. Sanity check on the trap: the tightest cell is exactly where a strong-threshold receiver meets a weak-swing driver ( $V_{O H}^{B} = 2.5 V ≳ V_{I H}^{A} = 2.4 V$ ), which matched our forecast. Note that had we (wrongly) paired A's output with A's own input, we would have computed a meaningless number that crosses no gate boundary — the classic exam mistake.

Active recall

Recall Match the cell to the symptom (reveal each answer after the

:::) Zero swing output ( $V_{O H} = V_{O L}$ ) — which cell and what does it mean? ::: Cell C5 (degenerate) — both margins are zero, the gate cannot restore levels. A margin comes out negative — what does that mean? ::: Cell C4 — logic levels overlap the forbidden band; the gate misreads even with no noise. A margin equals exactly $0 V$ — what is the status? ::: Cell C3 (knife-edge) — valid only with literally zero noise; treated as failed in practice. As $V_{D D} \to 0$ the ideal CMOS margin does what? ::: Cell C6 — it goes to $0 V$ linearly, because margin $= V_{D D} /2$ . Chained mismatched families — where is the danger? ::: Cell C8 — pair each driver output with the next gate's input; a weak-swing driver into a high-threshold receiver gives the tightest margin.

Connections

Noise margins (NMH, NML) — the parent note (formulas and their derivation).
CMOS Inverter VTC — where the four voltages come from.
Static Gain and Regenerative Property — governs Ex 5 (degenerate) and the sign of the margins.
Fan-out and Loading — degrades $V_{O H} / V_{O L}$ , the source of Ex 8-style weak edges.
Power Supply Scaling — the limit computed in Ex 6.
Static Noise Margin (SRAM butterfly curve) — the same min-margin idea in memory cells.