Noise margins (NMH, NML): Visual walkthrough — Hardware deep dive

This page re-derives the central result of Noise margins (NMH, NML) entirely from pictures. If a symbol appears, you will have seen it on a figure first.

Step 1 — What a logic gate actually does: the transfer curve

WHAT: the horizontal axis is $V_{in}$ (input voltage), the vertical axis is $V_{o u t}$ (output voltage). For an inverter, a low input gives a high output and vice-versa, so the curve slides from top-left down to bottom-right.

WHY: noise is just an unwanted change in $V_{in}$ . To know whether the gate survives noise, we must know how a change in $V_{in}$ turns into a change in $V_{o u t}$ — that relationship is the curve $f$ .

PICTURE: look at the falling S-curve. Flat at the top (a range of low inputs all give a high output), steep in the middle, flat at the bottom. The green arrow shows the "go up to the curve" reading of $f$ .

Step 2 — "Steepness" made precise: the slope, and why $- 1$ is magic

WHY a derivative and not just a ratio? Because the tilt is different at every point of the S-curve. A single ratio $V_{o u t} / V_{in}$ would average the whole thing; we need the tilt right here, locally — that is precisely the job of $\frac{d V _{o u t}}{d V _{in}}$ .

Now the key. Suppose a noise bump changes the input by a small amount $Δ V_{in}$ . The output changes by

$Δ V_{o u t} \approx local tilt \frac{d V _{o u t}}{d V _{in}} \times noise bump in Δ V_{in}$

$Δ V_{in}$ = the noise wiggle that arrived at the input.
$\frac{d V _{o u t}}{d V _{in}}$ = the multiplier the gate applies to it.
$Δ V_{o u t}$ = the wiggle that leaves the output and travels to the next gate.

The magic threshold: compare the size of the leaving wiggle to the arriving one.

If $∣ slope ∣ < 1$ → $∣Δ V_{o u t} ∣ < ∣Δ V_{in} ∣$ → noise shrinks.
If $∣ slope ∣ = 1$ → noise passes through unchanged — break-even.
If $∣ slope ∣ > 1$ → noise grows — disaster.

PICTURE: the two red dots mark where the tilt equals $- 1$ (negative because an inverter curve falls). Between them the gate amplifies; outside them it calms noise down.

Step 3 — Naming the two break-even points: $V_{I L}$ and $V_{I H}$

WHAT: two vertical marks on the input axis, dropped straight down from the two red dots of Step 2.

WHY these two and not any others: they are not chosen by taste — they are forced by the physics. Anywhere between them the gate amplifies noise, so no honest logic level can live there. The break-even points are the outermost edges where noise is still (barely) not amplified.

PICTURE: the strip between $V_{I L}$ and $V_{I H}$ is shaded as the "forbidden zone" — no valid logic level may sit inside it. The dashed line in the exact middle marks $V_{M}$ , the switching threshold where input equals output ( $V_{o u t} = V_{in}$ ) — the point the curve is racing through; we will need it in Step 8.

Step 4 — Reading the outputs those thresholds produce: $V_{O H}$ and $V_{O L}$

WHAT: stand on each threshold on the input axis, walk up to the curve, then across to the output axis. Where you land are $V_{O H}$ (high, from $V_{I L}$ ) and $V_{O L}$ (low, from $V_{I H}$ ).

WHY cross like that: $V_{I L}$ is a low input, and an inverter turns a low input into a high output — so the level a valid HIGH is guaranteed to reach is $f (V_{I L}) = V_{O H}$ . Symmetrically the highest valid-1 input $V_{I H}$ produces the lowest guaranteed output $f (V_{I H}) = V_{O L}$ .

PICTURE: two dashed "L-shaped" paths — up from $V_{I L}$ to the curve, then across to $V_{O H}$ ; and up from $V_{I H}$ , then across to $V_{O L}$ .

Step 5 — Chaining two gates: where noise actually attacks

WHAT: draw driver → wire → receiver. On the wire, an arrow shows noise being injected.

WHY: this is the single most-missed point. The safety cushion is the gap between "what the sender promises to output" and "what the receiver demands at its input". That gap spans a gate boundary.

PICTURE: the driver box outputs $V_{O H}$ ; noise (jagged arrow) pushes the wire voltage down; the receiver box has a horizontal line at $V_{I H}$ marking its "still counts as 1" floor.

Step 6 — The HIGH cushion: $N M_{H} = V_{O H} - V_{I H}$

WHAT: a HIGH signal leaves the driver at (at least) $V_{O H}$ . Noise can only drop it in the worst case. The receiver keeps calling it a 1 until it falls below $V_{I H}$ .

WHY the subtraction: the ceiling we start from is $V_{O H}$ , the floor we may not cross is $V_{I H}$ . The room to fall is their difference.

$N M_{H} = driver’s guaranteed high (start) V_{O H} - receiver’s high floor (limit) V_{I H}$

PICTURE: a vertical bracket on the voltage axis from $V_{I H}$ up to $V_{O H}$ — a downward arrow labelled "noise budget" fills it.

Step 7 — The LOW cushion: $N M_{L} = V_{I L} - V_{O L}$

WHAT: a LOW signal leaves the driver at (at most) $V_{O L}$ . Noise can only raise it. The receiver keeps calling it a 0 until it climbs above $V_{I L}$ .

WHY the order flips: for a LOW, noise pushes up, so now the ceiling is the receiver's limit $V_{I L}$ and the floor is the driver's start $V_{O L}$ . Larger minus smaller keeps the margin positive.

$N M_{L} = receiver’s low ceiling (limit) V_{I L} - driver’s guaranteed low (start) V_{O L}$

PICTURE: a vertical bracket from $V_{O L}$ up to $V_{I L}$ , with an upward arrow labelled "noise budget".

Step 8 — The degenerate cases: when a cushion collapses

WHAT & WHY: we must cover every scenario the reader could meet.

Zero margin ( $V_{O H} = V_{I H}$ or $V_{I L} = V_{O L}$ ): the bracket has height zero — any noise at all flips the bit. The logic is broken even in a "clean" lab.
Negative margin ( $V_{O H} < V_{I H}$ ): the driver's best HIGH is already below what the receiver demands. The gate misreads with no noise present. This is why both margins must be strictly positive.
Ideal CMOS limit: with huge gain the S-curve becomes a vertical cliff at the switching threshold $V_{M} = V_{D D} /2$ (defined in Step 3 as the point where output equals input), and the flat shoulders reach the rails: $V_{O H} \to V_{D D}$ , $V_{O L} \to 0$ , while $V_{I L} \approx V_{I H} \approx V_{M}$ . Then both cushions grow to $\approx V_{D D} /2$ — the widest, most balanced possible. This is exactly why CMOS wins (see Static Gain and Regenerative Property and CMOS Inverter VTC).

PICTURE: three mini-panels — collapsed (zero), inverted (negative, forbidden zones overlap the valid ranges), and ideal (fat balanced brackets).

The one-picture summary

Everything at once: the VTC, the two $- 1$ points, all four voltages, the forbidden zone, and both cushion-brackets on the same axes. The little flow along the top of the figure retraces the whole derivation, arrow by arrow, back to the figures that built each step.

Recall Feynman retelling — the whole walkthrough in plain words

I draw a curve showing what comes out of a gate for every voltage I put in — I call that rule $f$ , "go up to the curve and read the height". It's flat, then steep, then flat. On the flat parts the gate ignores little wiggles — that's where safe signals live. I find the two spots where the curve tilts at exactly one-to-one; before them wiggles shrink, after them wiggles blow up, so those spots are the outer fences of the safe zones. I call those input spots $V_{I L}$ (highest still-a-0) and $V_{I H}$ (lowest still-a-1). I walk each up to the curve and across to read the outputs they make: $V_{O H} = f (V_{I L})$ (a big output) and $V_{O L} = f (V_{I H})$ (a small one). Then I remember that a real signal is born at one gate's output and judged at the next gate's input, with noise sneaking in on the wire between. For a HIGH, noise can only pull it down, so the cushion is how far it can drop before it falls under $V_{I H}$ : that's $V_{O H} - V_{I H}$ . For a LOW, noise can only push it up, so the cushion is how far it can rise before it passes $V_{I L}$ : that's $V_{I L} - V_{O L}$ . If either cushion is zero or negative the chip is broken. Perfect CMOS makes the curve a cliff at $V_{M} = V_{D D} /2$ so both cushions are about half the battery voltage — that's why it's everywhere.

Connections

Noise margins (NMH, NML) — the parent result this page derives visually.
CMOS Inverter VTC — the curve of Step 1, from transistor physics.
Static Gain and Regenerative Property — why the $- 1$ points and high gain matter (Step 2, Step 8).
Fan-out and Loading — how loading erodes $V_{O H} / V_{O L}$ and shrinks the brackets.
Power Supply Scaling — lowering $V_{D D}$ shrinks the ideal $V_{D D} /2$ cushions.
Static Noise Margin (SRAM butterfly curve) — the same bracket idea for memory cells.

On the VTC, where do the input thresholds live?

At the two points where the slope

d V_{o u t} / d V_{in} = - 1

What does the mapping

f

mean in

V_{o u t} = f (V_{in})

"Stand at

V_{in}

, go up to the curve, read the output height" — the VTC written as a function.

How do you get

V_{O H}

from

V_{I L}

Map

V_{I L}

through the curve:

V_{O H} = f (V_{I L})

What is

V_{M}

The switching threshold, where output equals input (

V_{o u t} = V_{in}

); for ideal CMOS

V_{M} = V_{D D} /2

Why couple an output to the next gate's input?

Noise is added on the wire between a driver's output and a receiver's input, so the margin spans that boundary.

What does a zero noise margin mean physically?

The bracket has zero height — any noise at all flips the bit, even in a clean circuit.

What does a negative margin mean?

The driver's valid level already violates the receiver's threshold, so it misreads with no noise present.