Noise margins (NMH, NML): Question bank — Hardware deep dive

Symbol refresher — read this before the traps

Every trap below leans on the same nine symbols. If any of these feels fuzzy, the trap will beat you for the wrong reason. Here they are in plain words, all anchored to one picture.

Definition The players

$V_{D D}$ = the supply voltage, the highest voltage the chip's power rail delivers. It is the "ceiling of the room" every signal lives under.
$V_{O H}$ = output HIGH level: the voltage a driving gate guarantees when it sends a 1. Sits near the top rail.
$V_{O L}$ = output LOW level: the voltage a driving gate guarantees when it sends a 0. Sits near ground.
$V_{I H}$ = input HIGH threshold: the smallest input voltage the receiving gate still reads as a 1.
$V_{I L}$ = input LOW threshold: the largest input voltage the receiving gate still reads as a 0.
$V_{M}$ = the switching threshold: the input voltage where the inverter's output equals its input ( $V_{o u t} = V_{in}$ ), the "tipping point" of the curve.
$A_{v}$ = the voltage gain: how many volts the output moves per volt of input, i.e. the slope $d V_{o u t} / d V_{in}$ of the curve. $∣ A_{v} ∣$ is its size ignoring sign.
$N M_{H} = V_{O H} - V_{I H}$ = the HIGH noise margin, the downward cushion for a 1.
$N M_{L} = V_{I L} - V_{O L}$ = the LOW noise margin, the upward cushion for a 0.

The VTC (Voltage Transfer Characteristic) is just the graph of $V_{o u t}$ against $V_{in}$ for one inverter. Look at Figure 1: the S-shaped white curve is the VTC. The two points where its slope is exactly $- 1$ (the small amber marks) are, by definition, $V_{I L}$ (left) and $V_{I H}$ (right). Read the output off those points to get $V_{O H}$ and $V_{O L}$ .

True or false — justify

A wider noise margin always means a faster gate.

False. Margins measure static robustness (voltage cushion), not switching speed. A gate with a very sharp, high-gain VTC can have large margins yet be slow if it is heavily loaded — see Fan-out and Loading.

If a gate has

N M_{H} = 0.9

V it can absorb exactly 0.9 V of noise on any input without ever failing.

False in spirit.

N M_{H}

is the worst-case HIGH-side cushion; it only guards a signal that is genuinely HIGH and being pulled down. It says nothing about a LOW signal, which is guarded by

N M_{L}

Making both transistors symmetric (

β_{n} = β_{p}

) maximises the sum

N M_{H} + N M_{L}

False. Symmetry maximises the minimum of the two, not the sum. Skewing can raise one margin while lowering the other; the sum can stay similar, but the weakest link (the min) gets worse.

V_{O H}

and

V_{O L}

depend only on the driver, while

V_{I H}

and

V_{I L}

depend only on the receiver.

True. Output levels are what the driving gate guarantees; input thresholds are what the next gate demands. Noise margin couples the two across the wire.

Lowering

V_{D D}

leaves the noise margins unchanged because everything scales together.

False. Absolute margins shrink roughly with

V_{D D}

(about

V_{D D} /2

each in ideal CMOS), while physical noise sources like coupling do not scale down as neatly — see Power Supply Scaling.

A gate with negative

N M_{L}

can still work as long as

N M_{H}

is large.

False. A negative margin means a valid driver LOW already overlaps the receiver's forbidden band, so a LOW can be misread as HIGH even with zero noise. Robustness

= min (N M_{H}, N M_{L})

, so it is broken.

V_{I L}

and

V_{I H}

are chosen by the designer to give convenient margins.

False. They are defined by the

d V_{o u t} / d V_{in} = - 1

(i.e.

A_{v} = - 1

) unity-gain points of the actual VTC — they fall out of transistor physics, not preference. See CMOS Inverter VTC.

The noise margins on a datasheet fully describe how much noise a fast gate tolerates at any frequency.

False.

N M_{H}, N M_{L}

are static (DC) margins. At high speed, short spikes of capacitive coupling or kickback can be tolerated even if they briefly exceed the static margin, while sustained ringing can fail below it — dynamic behaviour is a separate story.

Spot the error

N M_{H} = V_{O H} - V_{O L}

, because those are the two output extremes."

Wrong term. HIGH margin must cross the gate boundary to the receiver's input threshold:

N M_{H} = V_{O H} - V_{I H}

. Subtracting two outputs never involves the next gate at all.

N M_{L} = V_{O L} - V_{I L}

, by analogy with the HIGH formula."

Sign error — this comes out negative. For a LOW, noise pushes the voltage up, so the receiver limit

V_{I L}

is the larger number:

N M_{L} = V_{I L} - V_{O L} > 0

"We pick the slope

= - 1

points because that is where the gate has maximum gain."

Not maximum — maximum

∣ A_{v} ∣

is at

V_{M}

. The

- 1

points are where

∣ A_{v} ∣

equals exactly one, the break-even boundary between noise being attenuated (

∣ A_{v} ∣ < 1

) and amplified (

∣ A_{v} ∣ > 1

), as Figure 1 shows.

"For a stored HIGH, noise is dangerous if it pushes the level upward toward

V_{D D}

Backwards. Pushing a HIGH higher only makes it more clearly a 1. The threat is noise pulling it down toward

V_{I H}

; that is what

N M_{H}

budgets for.

"CMOS has huge margins because its transistors have high gain, so

V_{O H}

can exceed

V_{D D}

The output cannot exceed the rail. CMOS margins are large because the swing is rail-to-rail (

V_{O H} \approx V_{D D}

V_{O L} \approx 0

) and the threshold sits near

V_{D D} /2

, not because of any over-rail output.

"If

∣ A_{v} ∣ < 1

everywhere, the gate still restores logic levels, just slowly."

No restoration at all. Restoration needs a region where

∣ A_{v} ∣ > 1

(so a marginal input is amplified back toward a rail); with

∣ A_{v} ∣ < 1

everywhere the curve is too flat to push signals to the rails — see Static Gain and Regenerative Property. Margins would collapse.

Why questions

Why does the HIGH margin subtract

V_{I H}

and not

V_{I L}

Because a HIGH signal is only ever tested against the receiver's HIGH-recognition floor,

V_{I H}

— the lowest voltage still read as 1.

V_{I L}

is the LOW side's business.

Why is overall robustness the minimum of the two margins rather than the average?

A chip fails at its weakest point. The average could look healthy while one side is near zero; the min exposes the real failure threshold — the smaller cushion is the one noise will breach first.

Why must both margins be strictly positive, not merely non-negative?

At exactly zero, the guaranteed output sits on the receiver's threshold with no cushion — any noise at all, or normal manufacturing spread, tips it into misreading.

Why does the SRAM butterfly curve reuse this same margin idea?

A bit-cell is two cross-coupled inverters; its stability is the largest square that fits between the mirrored VTCs, which is a static noise margin of the very same "how much noise before the state flips" flavour — see Static Noise Margin (SRAM butterfly curve).

Why does heavier fan-out erode the margins?

Extra load and leakage pull

V_{O H}

down and

V_{O L}

up (the swing degrades from the rails), which directly shrinks both

V_{O H} - V_{I H}

and

V_{I L} - V_{O L}

— see Fan-out and Loading.

Why can't we simply widen the forbidden band to get bigger margins for free?

The forbidden band lives between

V_{I L}

and

V_{I H}

(Figure 2), which are fixed by the VTC's

A_{v} = - 1

slopes. Widening it means changing the transistor design, not relabelling — the physics sets those points.

Why does weakening the PMOS (

β_{p} < β_{n}

) move

V_{M}

down?

The NMOS then wins the pull-down tug-of-war at a lower input voltage, so the output flips earlier and the whole switching point

V_{M}

slides toward ground — see CMOS Inverter VTC.

Edge cases

What are the margins if the VTC is a perfectly vertical step at

V_{M}

(infinite gain)?

Then

V_{I L} = V_{I H} = V_{M}

and, with rail outputs,

N M_{H} = V_{D D} - V_{M}

N M_{L} = V_{M} - 0

. This is the idealised symmetric case giving

\approx V_{D D} /2

each — the theoretical best.

What happens to the margins if the gate has gain

∣ A_{v} ∣ < 1

everywhere (no

A_{v} = - 1

crossings exist)?

V_{I L}

and

V_{I H}

become ill-defined and the valid logic ranges collapse; effectively there is no reliable noise margin because the gate never restores levels.

A skewed inverter has

V_{M}

pushed very close to ground. Which margin is at risk?

N M_{L} = V_{I L} - V_{O L}

shrinks because its ceiling

V_{I L}

drops with

V_{M}

, while

N M_{H}

grows — the LOW side becomes the weak link.

What is the noise margin of two gates whose

V_{O H}

equals the next gate's

V_{I H}

exactly?

N M_{H} = 0

. The system is on the knife-edge — logically it "works" with zero noise but any disturbance fails it, so it is treated as broken in practice.

If a driver's

V_{O L}

rises above the receiver's

V_{I L}

(e.g. severe loading), what does

N M_{L}

signal?

N M_{L}

goes negative, meaning a driven LOW already exceeds the largest voltage read as 0 — the receiver may latch it as a 1 with no noise present at all.

Does a symmetric CMOS inverter guarantee equal margins across every input pattern in a real chip?

No — process variation, temperature, and unequal wire coupling make the effective

V_{O H} / V_{O L}

and thresholds drift, so nominal symmetry only gives approximately balanced margins.

How can a fast switching aggressor wire hurt a victim even when its static noise margin is comfortable?

Capacitive coupling ("kickback") injects a brief spike whose height depends on the aggressor's edge rate, not its DC level; a fast edge can momentarily push the victim past

V_{I H}

V_{I L}

even though a slow signal at the same level would be safe — a dynamic, frequency-dependent margin.

Are static noise margins enough to guarantee a flip-flop never captures a wrong value?

No. Even with perfect voltage margins, a data change too close to the clock edge violates setup/hold timing and can drive the flop into metastability — a valid-voltage failure that noise margins do not cover; it is a timing margin, a separate axis of robustness.

Connections

CMOS Inverter VTC — the source of every voltage used here.
Static Gain and Regenerative Property — why $∣ A_{v} ∣ > 1$ is required for real margins.
Fan-out and Loading — how loading eats the margins.
Power Supply Scaling — why lower $V_{D D}$ shrinks the cushions.
Static Noise Margin (SRAM butterfly curve) — the same principle for bit-cells.

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