Noise margins (NMH, NML): Exercises — Hardware deep dive

Before we start, the two facts everything rests on — copy them onto scrap paper:

Here is the picture we will keep pointing back to — the "voltage stack" that shows where the two cushions live:

Level 1 — Recognition

L1.1

Given the labels $V_{O H} = 2.4$ V, $V_{I H} = 2.0$ V. Which formula gives the HIGH noise margin, and what is its value?

Recall Solution

WHAT: we need $N M_{H}$ . WHY that formula: a HIGH travels driver→receiver; the driver sits at least at $V_{O H}$ and the receiver needs at least $V_{I H}$ , so the room for noise is the drop from ceiling to floor. $N M_{H} = V_{O H} - V_{I H} = 2.4 - 2.0 = 0.4 V$ On the stack (figure s01) this is the blue gap. Positive → valid.

L1.2

Given $V_{I L} = 0.8$ V, $V_{O L} = 0.4$ V. Write the LOW noise margin formula and compute it.

Recall Solution

WHY this order: a LOW is threatened by noise pushing it up, so the limit is $V_{I L}$ (the larger number) and the start is $V_{O L}$ . $N M_{L} = V_{I L} - V_{O L} = 0.8 - 0.4 = 0.4 V$ Pink gap on the stack. Positive → valid.

L1.3

True or false: overall robustness of a gate is $N M_{H} + N M_{L}$ .

Recall Solution

False. Robustness is $min (N M_{H}, N M_{L})$ , not the sum. WHY: a chain fails at its weakest link. If the LOW cushion is tiny, a big HIGH cushion cannot save you — noise that flips a 0 still breaks the logic. So the gate is only as safe as its smaller margin.

Level 2 — Application

L2.1

A logic family specifies $V_{O H} = 4.6$ V, $V_{I H} = 3.5$ V, $V_{I L} = 1.0$ V, $V_{O L} = 0.4$ V. Compute $N M_{H}$ , $N M_{L}$ , and the robustness.

Recall Solution

$N M_{H} = 4.6 - 3.5 = 1.1 V$ $N M_{L} = 1.0 - 0.4 = 0.6 V$ Robustness $= min (1.1, 0.6) = 0.6 V$ — the LOW side is weaker, so this gate tolerates only $0.6$ V of noise in the worst case. Both positive → valid logic.

L2.2

An ideal symmetric CMOS inverter runs at $V_{D D} = 1.8$ V with rail-to-rail output ( $V_{O H} = 1.8$ V, $V_{O L} = 0$ V) and a sharp threshold, so $V_{I H} \approx V_{I L} \approx V_{M} = V_{D D} /2 = 0.9$ V. Find both margins.

Recall Solution

$N M_{H} = V_{O H} - V_{I H} = 1.8 - 0.9 = 0.9 V$ $N M_{L} = V_{I L} - V_{O L} = 0.9 - 0 = 0.9 V$ Both equal $V_{D D} /2 = 0.9$ V. This balanced pair is why CMOS dominates — rail-to-rail swing plus a centred threshold. See CMOS Inverter VTC for where the $0.9$ V threshold comes from.

L2.3

Same family as L2.1 but the supply noise erodes the driver's high output to $V_{O H} = 4.2$ V (everything else unchanged). New $N M_{H}$ ? Did robustness change?

Recall Solution

$N M_{H} = 4.2 - 3.5 = 0.7 V$ $N M_{L}$ is untouched: still $1.0 - 0.4 = 0.6$ V. Robustness $= min (0.7, 0.6) = 0.6 V$ — unchanged, because the weak link was already the LOW side. The HIGH degradation hurt $N M_{H}$ but not yet enough to become the worst case. (See Fan-out and Loading for what erodes $V_{O H}$ .)

Level 3 — Analysis

L3.1

A designer weakens the PMOS, moving the switching threshold down to $V_{M} = 0.6$ V while keeping rails at $V_{O H} = 1.8$ V, $V_{O L} = 0$ V. Using the sharp-VTC approximation $V_{I H} \approx V_{I L} \approx V_{M}$ , predict before computing which margin grows and which shrinks. Then compute.

Recall Solution

Predict: lowering $V_{M}$ lowers both input thresholds. $N M_{L} = V_{I L} - V_{O L}$ has its ceiling drop → shrinks. $N M_{H} = V_{O H} - V_{I H}$ has the subtracted term drop → grows. Compute ( $V_{I H} = V_{I L} = 0.6$ ): $N M_{L} = 0.6 - 0 = 0.6 V (down from 0.9)$ $N M_{H} = 1.8 - 0.6 = 1.2 V (up from 0.9)$ Confirmed. Robustness $= min (1.2, 0.6) = 0.6$ V — worse than the balanced $0.9$ V. Skew trades one margin for the other; it never gives both for free.

L3.2

Refer to the tilt diagram below. It shows the symmetric case and the PMOS-weakened case side by side.

Using the figure, explain in one sentence why the minimum margin can only stay equal or get worse when you skew away from symmetry.

Recall Solution

As $V_{M}$ slides off-centre, one cushion opens and the other closes by the same amount (the threshold moves the same distance from both rails combined). The smaller cushion is what $min$ reads, and moving off-centre can only make the smaller one smaller — so $min$ is maximised exactly at symmetry ( $V_{M} = V_{D D} /2$ ). This is the design rule: centre the threshold to maximise the worst-case margin.

L3.3

A gate has $N M_{H} = 0.9$ V and $N M_{L} = 0.9$ V. A neighbouring aggressor wire couples a downward noise spike of $0.7$ V onto a HIGH line and, separately at another time, an upward spike of $1.1$ V onto a LOW line. Which event (if any) causes a logic failure?

Recall Solution

A HIGH survives downward noise up to $N M_{H} = 0.9$ V. The $0.7$ V downward spike $< 0.9$ V → HIGH survives. A LOW survives upward noise up to $N M_{L} = 0.9$ V. The $1.1$ V upward spike $> 0.9$ V → LOW fails: the level is pushed above $V_{I L}$ into the forbidden region and may be misread as a 1. Only the LOW event breaks the logic.

Level 4 — Synthesis

L4.1

Two supplies are compared. Assume ideal symmetric CMOS: $V_{O H} = V_{D D}$ , $V_{O L} = 0$ , threshold at $V_{D D} /2$ . Compute robustness at $V_{D D} = 1.8$ V and at $V_{D D} = 0.9$ V. Express the ratio and comment (link to Power Supply Scaling).

Recall Solution

At $V_{D D} = 1.8$ : both margins $= 1.8/2 = 0.9$ V → robustness $0.9$ V. At $V_{D D} = 0.9$ : both margins $= 0.9/2 = 0.45$ V → robustness $0.45$ V. Ratio $= 0.45/0.9 = 0.5$ . Comment: absolute noise margin scales linearly with $V_{D D}$ ; halving the supply halves the cushion. Since coupled noise does not shrink as fast, low- $V_{D D}$ chips are inherently more fragile — the core worry of supply scaling.

L4.2

A driver feeds a receiver from a different logic family. Driver guarantees $V_{O H} = 2.4$ V, $V_{O L} = 0.4$ V. Receiver demands $V_{I H} = 1.6$ V, $V_{I L} = 1.2$ V. Are the two families compatible (both margins positive)? Compute both.

Recall Solution

The margin formulas span the gate boundary, so we mix the driver's outputs with the receiver's inputs directly: $N M_{H} = V_{O H} - V_{I H} = 2.4 - 1.6 = 0.8 V > 0 ✓$ $N M_{L} = V_{I L} - V_{O L} = 1.2 - 0.4 = 0.8 V > 0 ✓$ Both positive → the families are compatible, with a balanced $0.8$ V of tolerance on each side.

L4.3

A gate has $N M_{L} = 0.6$ V. Loading (fan-out) raises the driver's low output from $V_{O L} = 0.4$ V to $V_{O L} = 0.55$ V while $V_{I L} = 1.0$ V stays fixed. What is the new $N M_{L}$ , and how much LOW-side headroom was consumed by loading?

Recall Solution

New margin: $N M_{L} = V_{I L} - V_{O L} = 1.0 - 0.55 = 0.45 V$ Headroom consumed $= 0.60 - 0.45 = 0.15$ V — exactly the $0.15$ V rise in $V_{O L}$ (from $0.4$ to $0.55$ ). WHY it maps 1:1: $N M_{L}$ depends on $V_{O L}$ with a coefficient of $- 1$ , so every millivolt $V_{O L}$ climbs eats one millivolt of LOW margin. This is precisely how Fan-out and Loading erodes robustness.

Level 5 — Mastery

L5.1

Prove that for the sharp-VTC symmetric model ( $V_{O H} = V_{D D}$ , $V_{O L} = 0$ , $V_{I H} = V_{I L} = V_{M}$ ), the robustness $R (V_{M}) = min (V_{D D} - V_{M}, V_{M})$ is maximised at $V_{M} = V_{D D} /2$ , and state the maximum.

Recall Solution

Set up: $N M_{H} = V_{D D} - V_{M}$ (a decreasing line in $V_{M}$ ) and $N M_{L} = V_{M} - 0 = V_{M}$ (an increasing line). $R (V_{M}) = min$ of the two. Where do they cross? Set them equal: $V_{D D} - V_{M} = V_{M} \Rightarrow V_{M} = V_{D D} /2$ . Why the crossing is the max: for $V_{M} < V_{D D} /2$ , the smaller line is $N M_{L} = V_{M}$ , which rises as $V_{M}$ increases → push $V_{M}$ up. For $V_{M} > V_{D D} /2$ , the smaller line is $N M_{H} = V_{D D} - V_{M}$ , which falls as $V_{M}$ increases → push $V_{M}$ down. Both pressures point to the crossing. So the $min$ peaks exactly where the two lines meet. Maximum value: $R (V_{D D} /2) = V_{D D} /2$ . This is the analytic backbone of "symmetric design maximises the minimum margin." The two-line picture is figure s03 below.

L5.2

Design task. You must ship a gate with robustness $\geq 0.5$ V at $V_{D D} = 1.2$ V, rail-to-rail ( $V_{O H} = 1.2$ , $V_{O L} = 0$ ). Using the sharp symmetric model, what range of $V_{M}$ satisfies the spec?

Recall Solution

Need $min (V_{D D} - V_{M}, V_{M}) \geq 0.5$ , i.e. both: $V_{M} \geq 0.5 and V_{D D} - V_{M} \geq 0.5 \Rightarrow V_{M} \leq 0.7$ So $V_{M} \in [0.5, 0.7]$ V. The centre $V_{M} = 0.6$ V gives the best margin ( $0.6$ V); anywhere in $[0.5, 0.7]$ still meets the $0.5$ V spec. (Compare against the SRAM-cell version of this reasoning in Static Noise Margin (SRAM butterfly curve).)

L5.3

Synthesis + physics. The reason the $- 1$ slope points define $V_{I L}, V_{I H}$ is that between them the inverter has $∣ A_{v} ∣ > 1$ (gain magnitude above unity), which regenerates levels. A weak inverter with peak gain $∣ A_{v} ∣ = 0.9$ (never exceeds 1) is proposed. Explain what happens to the noise margins and whether valid logic is possible.

Recall Solution

If the VTC slope magnitude never reaches $1$ , there are no $- 1$ points → $V_{I L}$ and $V_{I H}$ are not well-defined by the usual rule; the "valid" HIGH and LOW regions never fully separate. WHY it fails: with $∣ A_{v} ∣ < 1$ everywhere, the gate attenuates the swing instead of restoring it, so noise is never fully rejected and levels degrade down the chain. Effectively the margins collapse (they can go to zero or negative), and reliable digital logic is impossible. This is exactly the Static Gain and Regenerative Property: you need $∣ A_{v} ∣ > 1$ somewhere to snap a noisy input back to a clean rail. The $- 1$ points, and hence the margins, only exist because the gain crosses unity.

Wrap-up recall

Recall One-line answers to the whole ladder

L1: pick the right formula (H with H, L with L), robustness is $min$ not $+$ . L2: $N M_{H} = V_{O H} - V_{I H}$ , $N M_{L} = V_{I L} - V_{O L}$ ; symmetric CMOS gives $V_{D D} /2$ each. L3: skew trades margins, lowering the $min$ ; noise fails whichever cushion it exceeds. L4: formulas cross the gate boundary (mixed families fine); margins scale with $V_{D D}$ ; loading eats $N M_{L}$ 1:1 with $V_{O L}$ . L5: $min$ peaks at $V_{M} = V_{D D} /2$ giving $R = V_{D D} /2$ ; you need $∣ A_{v} ∣ > 1$ for margins to exist at all.

Connections

Noise margins (NMH, NML) (index 3.2.6) — the parent theory these drills exercise.
CMOS Inverter VTC — origin of $V_{I L}, V_{I H}, V_{M}$ .
Static Gain and Regenerative Property — why $∣ A_{v} ∣ > 1$ is required (L5.3).
Fan-out and Loading — erodes $V_{O L} / V_{O H}$ (L2.3, L4.3).
Power Supply Scaling — margins scale with $V_{D D}$ (L4.1).
Static Noise Margin (SRAM butterfly curve) — same $min$ -of-two-cushions idea in bit-cells.

Robustness of a gate is the sum or the min of the two margins?

The

min (N M_{H}, N M_{L})

— a chain fails at its weakest link.

For mismatched families, does the margin formula change?

No —

N M_{H} = V_{O H} (driver) - V_{I H} (receiver)

; just use each family's own levels.

At what

V_{M}

is worst-case margin maximised (symmetric model)?

V_{M} = V_{D D} /2

, giving robustness

V_{D D} /2

V_{O L}

rises by

0.15

V, how much

N M_{L}

is lost?

Exactly

0.15

V —

N M_{L}

falls 1:1 with

V_{O L}

Can a gate with peak gain

∣ A_{v} ∣ = 0.9

give valid logic?

No — without

∣ A_{v} ∣ > 1

there are no

- 1

points, levels are not regenerated, margins collapse.