Noise margins (NMH, NML)

3.2.6 · Hardware › CMOS Circuit Design

Chapter: CMOS Circuit Design · Subtopic: Robustness of digital logic levels

Core idea

WHY yeh exist karta hai: kyunki "0" aur "1" points nahi hain, yeh voltage ke ranges hain. Sender ki promise aur receiver ki expectation ke beech ka gap hi margin hai.

WHAT yeh measure karta hai: worst-case tolerable noise, do parts mein — HIGH noise margin (NMH) aur LOW noise margin (NML).

HOW hum ise lete hain: transfer characteristic (VTC) par define kiye gaye char voltage levels se: $V_{O H}, V_{O L}, V_{I H}, V_{I L}$ .

Margins ko first principles se derive karna

Hum driver → receiver chain karte hain. Driver ek valid level output karta hai; receiver ko ise accept karna hoga chahe noise add ho jaaye.

Case HIGH (ek 1 wire se travel karta hai): Driver at least $V_{O H}$ guarantee karta hai. Receiver tab bhi ise 1 kahega jab tak uska input $V_{I H}$ se upar rahe. Noise sirf received voltage ko drop kar sakti hai (worst case). Tolerable drop:

$N M_{H} = V_{O H} - V_{I H}$

Yeh subtraction kyun? $V_{O H}$ wo ceiling hai jahan se hum shuru karte hain, $V_{I H}$ wo floor hai jo receiver ko chahiye. Dono ke beech ki distance hi yeh hai ki noise signal ko kitna neeche kheench sakti hai failure se pehle.

Case LOW (ek 0 wire se travel karta hai): Driver at most $V_{O L}$ guarantee karta hai. Receiver tab bhi ise 0 kahega jab tak uska input $V_{I L}$ se neeche rahe. Noise sirf ise upar uthaa sakti hai. Tolerable rise:

$N M_{L} = V_{I L} - V_{O L}$

Yeh order kyun? Ab $V_{I L}$ ceiling hai (receiver limit) aur $V_{O L}$ floor hai (driver start); noise low signal ko limit ki taraf upar dhakelta hai.

Worked example 1 — generic numbers

Given: $V_{O H} = 4.6 V, V_{I H} = 3.5 V, V_{I L} = 1.0 V, V_{O L} = 0.4 V$ .

$N M_{H} = 4.6 - 3.5 = 1.1 V$ Kyun: guaranteed high (4.6) se shuru karo, receiver ko jo minimum chahiye (3.5) wo ghatao.

$N M_{L} = 1.0 - 0.4 = 0.6 V$ Kyun: receiver 1.0 V tak 0 tolerate karta hai; driver 0.4 V par hai, isliye 0.6 V ki upward noise allowed hai.

Robustness $= min (1.1, 0.6) = 0.6$ V — LOW side kamzor hai.

Worked example 2 — ideal CMOS inverter (matched)

Worked example 3 — Forecast then Verify

Common mistakes

Active recall

Recall Reveal karne se pehle try karo

Memory se do margin formulas batao.
Slope = −1 points kyun?
Kis direction mein noise ek HIGH signal ko threaten karti hai?
CMOS margin roughly $V_{D D} /2$ kyun hai?

Answers: 1) $N M_{H} = V_{O H} - V_{I H}$ , $N M_{L} = V_{I L} - V_{O L}$ . 2) Noise attenuation aur amplification ke beech ki boundary. 3) Downward ( $V_{I H}$ ki taraf kheenchti hai). 4) Rail-to-rail swing + threshold at $V_{D D} /2$ .

Recall Feynman: ek 12-saal ke bachche ko explain karo

Socho tum ek note pass kar rahe ho jo "HIGH" ya "LOW" kehta hai. Tumhare dost ke kaano mein thodi fuzzy sunaai deta hai. Agar tum "HIGH" bahut zor se CHILLAO (top ke paas), toh bhi agar kuch noise ise thoda quiet kar de, tumhara dost phir bhi "HIGH" sunegaa. Jitni extra loudness tum spare kar sakte ho apne dost ke confuse hone se pehle, wahi noise margin hai. HIGH ke liye ek cushion hai (chillana) aur LOW ke liye ek (whisper karna). Ek achha chip dono cushions ko bada rakhta hai taaki random buzzing kabhi 1 ko 0 na bana sake.

Connections

CMOS Inverter VTC — jahan se $V_{I L}, V_{I H}, V_{M}$ aate hain.
Static Gain and Regenerative Property — kyun $∣ A_{v} ∣ > 1$ near $V_{M}$ levels restore karta hai.
Fan-out and Loading — $V_{O H} / V_{O L}$ ko degrade karta hai, margins ko erode karta hai.
Power Supply Scaling — lower $V_{D D}$ absolute margins ko shrink karta hai.
Static Noise Margin (SRAM butterfly curve) — wohi idea bit-cells par apply hota hai.

Noise margin kya hai?

Woh maximum input noise voltage jo ek gate tolerate kar sakta hai aur phir bhi valid output level produce karta hai.

HIGH noise margin ka formula?

N M_{H} = V_{O H} - V_{I H}

LOW noise margin ka formula?

N M_{L} = V_{I L} - V_{O L}

VTC par

V_{I L}

aur

V_{I H}

kaise define hote hain?

Woh input voltages jahan

d V_{o u t} / d V_{in} = - 1

hota hai (unity-gain points).

Slope = −1 points kyun choose karte hain?

Yeh us region ko separate karte hain jahan gate noise attenuate karta hai aur jahan amplify karta hai.

Stored HIGH ko noise kis direction mein threaten karti hai?

Downward — yeh level ko

V_{I H}

ki taraf kheenchti hai.

Stored LOW ko noise kis direction mein threaten karti hai?

Upward — yeh level ko

V_{I L}

ki taraf dhakelta hai.

Gate ki overall robustness?

min (N M_{H}, N M_{L})

Ideal symmetric CMOS inverter ke approximate margins?

Lagbhag

V_{D D} /2

each (rail-to-rail swing, threshold at

V_{D D} /2

Dono margins positive kyun hone chahiye?

Ek non-positive margin ka matlab hai ki valid logic levels forbidden region se overlap karte hain → gate bina noise ke bhi galat padh sakta hai.

Inverter threshold ko skew karne ka margins par effect?

Ek margin badhta hai aur doosra shrink hota hai; symmetric design minimum margin ko maximise karta hai.