Voltage transfer characteristic (VTC): Question bank

Before we start, one shared vocabulary reminder so no symbol is unearned. Keep the labeled VTC picture below in view — every "region A/B/C" and "45° line" reference points back to it.

$V_{in}$ = the voltage you feed the inverter's input (the gate of both transistors).
$V_{o u t}$ = the voltage the inverter produces at its output node.
$V_{D D}$ = the supply rail (the "full ON" high voltage); GND = 0 V.
$I_{D N}$ = the NMOS drain current (the pull-down current toward GND); $I_{D P}$ = the PMOS drain current (the pull-up current from $V_{D D}$ ).
$C$ = the output-node capacitance — all the stray/load capacitance hanging on $V_{o u t}$ . Its charging law is $I = C \frac{d V _{o u t}}{d t}$ ; in DC steady state $d V_{o u t} / d t = 0$ , so $C$ draws no current.
$V_{T n}$ = the NMOS threshold voltage, a positive number: the NMOS starts conducting once $V_{GS n}$ climbs above $V_{T n}$ .
$V_{T p}$ = the PMOS threshold voltage. By convention for a PMOS $V_{T p}$ is a negative number, so we always write its magnitude $∣ V_{T p} ∣$ : the PMOS starts conducting once its source-to-gate voltage $V_{S Gp} = V_{D D} - V_{in}$ exceeds $∣ V_{T p} ∣$ . Using $∣ V_{T p} ∣$ everywhere keeps all overdrive terms positive and removes any sign ambiguity.
$V_{GS n}$ = NMOS gate-to-source voltage (here $= V_{in}$ ); the overdrive is $V_{GS n} - V_{T n}$ , i.e. "how far past threshold you drive the gate" — the quantity that actually sets the current.
$β_{n}, β_{p}$ = the transistor strength (transconductance) factors: $β_{n} = k_{n}^{'} \frac{W _{n}}{L _{n}}$ for the NMOS and $β_{p} = k_{p}^{'} \frac{W _{p}}{L _{p}}$ for the PMOS, where $k^{'}$ is the process gain per unit shape and $W / L$ is the width-to-length ratio you draw. Bigger $β$ = the device pushes more current for the same overdrive = "stronger".
$r = β_{p} / β_{n}$ = "PMOS-to-NMOS strength ratio", $r > 1$ means the pull-up (PMOS) is stronger.
"Slope" always means $d V_{o u t} / d V_{in}$ , how fast the output falls as the input rises — for an inverter it is negative.

Below is the map every question refers to: the labeled VTC with its five regions (A–E), the near-vertical transition (C), and the 45° line whose crossing defines $V_{M}$ .

Figure — Voltage transfer characteristic (VTC)

Definition

The five regions, their input ranges, and conduction modes (NMOS state / PMOS state), for a rising sweep of $V_{in}$ from $0$ to $V_{D D}$ :

Region	$V_{in}$ range	NMOS	PMOS	$V_{o u t}$
A	$0 \leq V_{in} < V_{T n}$	cutoff	triode	$\approx V_{D D} = V_{O H}$
B	$V_{T n} \leq V_{in} < V_{M}$	saturation	triode	high, dropping
C	near $V_{M}$	saturation	saturation	steep near-vertical drop
D	$V_M<V_{in}\le V_{DD}-	V_{Tp}	$	triode
E	$V_{in}>V_{DD}-	V_{Tp}	$	triode

"Cutoff" = off, no current. "Triode" = on and behaving like a small resistor to a rail. "Saturation" = on and behaving like a current source (weakly dependent on $V_{o u t}$ ).

Formula

Where the $V_{M}$ formula comes from (used all over this page). At $V_{M}$ we have $V_{in} = V_{o u t} = V_{M}$ , and the region table says both devices are in saturation, so we use the square-law saturation currents: $I_{D N} = \frac{1}{2} β_{n} (V_{M} - V_{T n})^{2}, I_{D P} = \frac{1}{2} β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)^{2}$ Step 1 — set them equal (KCL at the output, the defining VTC constraint $I_{D N} = I_{D P}$ ): $\frac{1}{2} β_{n} (V_{M} - V_{T n})^{2} = \frac{1}{2} β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)^{2}$ Step 2 — take the square root of both sides (both sides are perfect squares, and every overdrive term is positive, so the roots are real and positive): $β_{n} (V_{M} - V_{T n}) = β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)$ Step 3 — divide by $β_{n}$ , introducing $r = β_{p} / β_{n}$ : $V_{M} - V_{T n} = r (V_{D D} - V_{M} - ∣ V_{T p} ∣)$ Step 4 — collect the $V_{M}$ terms ( $V_{M} + r V_{M} = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣)$ ) and divide by $(1 + r)$ : $V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}$ That linear-in- $V_{M}$ shortcut is the whole reason we square-rooted in Step 2.

True or false — justify

Recall A CMOS inverter VTC always passes through the point

$(V_{D D} /2, V_{D D} /2)$ . False. It passes through $(V_{M}, V_{M})$ by definition, and $V_{M} = V_{D D} /2$ only when $β_{n} = β_{p}$ and $V_{T n} = ∣ V_{T p} ∣$ ; a weaker PMOS pushes $V_{M}$ below the midpoint.

Recall At the switching threshold

$V_{M}$ , exactly one transistor conducts while the other is off. False. Both conduct and both sit in saturation — the drain currents $I_{D N}$ and $I_{D P}$ are equal and nonzero, which is precisely why current balance can pin $V_{o u t} = V_{M}$ .

Recall In the steep transition region the output node is momentarily floating (high-impedance).

False. Both transistors are ON as saturated current sources; KCL ( $I_{D N} = I_{D P}$ ) fully determines $V_{o u t}$ . It is highly sensitive, not undefined.

Recall The magnitude of the VTC slope at

$V_{M}$ can be less than 1 for a working inverter. False for logic use. Restoring logic needs $∣ slope ∣ > 1$ in the transition so that noise wiggles shrink; a slope magnitude below 1 there would amplify noise and destroy the digital abstraction.

Recall

$V_{O H}$ (the guaranteed output-high level) equals $V_{D D}$ exactly. Approximately, not exactly in general, but for a static CMOS inverter it truly rails: in region A the PMOS is in triode with zero current, so no IR drop leaves $V_{o u t} = V_{D D}$ . We write $V_{O H} \approx V_{D D}$ for safety with loads.

Recall If you swap the NMOS and PMOS widths, the VTC shape is unchanged.

False. Swapping widths changes $r = β_{p} / β_{n}$ , which shifts $V_{M}$ and skews the curve left or right; only the two rail heights $V_{O H}, V_{O L}$ stay put.

Recall The VTC is a dynamic (time-dependent) curve showing the switching waveform.

False. It is a steady-state DC relationship — every point assumes the output capacitor is fully charged ( $C d V_{o u t} / d t = 0$ ), so no time appears. Switching speed is Propagation Delay, a different topic.

Recall Increasing

$V_{D D}$ leaves the fractional switching point $V_{M} / V_{D D}$ unchanged. False in general. Because $V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}$ contains fixed thresholds, scaling $V_{D D}$ up moves $V_{M} / V_{D D}$ toward $r / (1 + r)$ ; the thresholds' relative weight shrinks.

Spot the error

Recall "Since the inverter has gain, its noise-margin points satisfy

$d V_{o u t} / d V_{in} = + 1$ ." The sign is wrong. An inverter's slope is negative, so the unity-gain points are where slope $= - 1$ ; using $+ 1$ finds no point on the curve at all.

Recall "Region C is bad because both transistors are on and waste power, so we should design

$V_{M}$ to avoid it." You can't avoid it — every valid $V_{in}$ sweep passes through region C once. The short-circuit (Short-circuit Power Dissipation) current spike is a real cost, but the steep gain there is required to restore logic levels; you minimise time spent there with fast edges, not by removing the region.

Recall "To center

$V_{M}$ , make the PMOS narrower than the NMOS because PMOS carries holes." Backwards. Holes are slower ( $k_{p}^{'} < k_{n}^{'}$ ), so the PMOS is intrinsically weaker; you must make it wider ( $W_{p} > W_{n}$ ) to reach $β_{p} = β_{n}$ and center $V_{M}$ .

Recall "At

$V_{in} = 0$ the NMOS is off, so $V_{o u t}$ is undefined." With NMOS cutoff the PMOS is fully on in triode and ties the output to $V_{D D}$ ; $V_{o u t} = V_{D D}$ , perfectly defined. A single OFF device does not float a node if the other device holds it to a rail.

Recall "The saturation current uses

$(V_{GS} - V_{T})$ , so at $V_{M}$ the NMOS current is $\frac{1}{2} β_{n} (V_{M} - V_{D D})^{2}$ ." Wrong overdrive. The NMOS gate overdrive is $V_{GS n} - V_{T n} = V_{in} - V_{T n} = V_{M} - V_{T n}$ , not $V_{M} - V_{D D}$ . Confusing which threshold belongs to which device is the classic $V_{M}$ derivation slip.

Recall "Noise margin

$N M_{H} = V_{I H} - V_{O L}$ ." Mismatched levels. $N M_{H}$ compares the high worlds: $N M_{H} = V_{O H} - V_{I H}$ . Mixing a high-output level with a low-related level gives a meaningless number; $N M_{L} = V_{I L} - V_{O L}$ is the low counterpart.

Recall "Because both currents are set equal, the inverter always draws steady DC current."

Only inside the transition does both-on current flow; at the rails one device is cutoff, so static current is ~0. The equal-current constraint ( $I_{D N} = I_{D P}$ ) is a balance condition per point, not a claim of constant conduction.

Why questions

Recall Why must

$I_{D N} = I_{D P}$ at every VTC point? The two transistors sit in series between $V_{D D}$ and GND, and in DC steady state the output-node capacitance $C$ draws no current ( $C d V_{o u t} / d t = 0$ ), so the only current path forces the two drain currents ( $I_{D N}$ pulling down, $I_{D P}$ pulling up) to be identical.

Recall Why does a stronger PMOS (larger

$r$ ) push $V_{M}$ toward $V_{D D}$ ? A stronger pull-up wins the tug-of-war for longer, holding $V_{o u t}$ high until $V_{in}$ climbs higher, so the crossover with the 45° line happens at a larger voltage.

Recall Why is the transition (region C) so nearly vertical?

Both devices behave as saturated current sources whose currents depend weakly on $V_{o u t}$ ; to keep the two equal, a tiny change in $V_{in}$ demands a large change in $V_{o u t}$ , i.e. huge $∣ d V_{o u t} / d V_{in} ∣$ .

Recall Why do we care where the slope equals exactly

$- 1$ and not some other value? At $∣ slope ∣ = 1$ an input wiggle produces an equal output wiggle — the break-even between the gate shrinking noise (inside, $∣ slope ∣ > 1$ ) and growing it (outside, $∣ slope ∣ < 1$ ). Those points bound the safe logic levels for Noise Margins.

Recall Why does taking the square root of both saturation-current equations simplify the

$V_{M}$ derivation? Each side is a perfect square in the overdrive voltage ( $V_{GS n} - V_{T n}$ and its PMOS counterpart); the square root turns quadratics into linear expressions in $V_{M}$ , so you can collect $V_{M}$ terms and solve directly instead of using the quadratic formula.

Edge cases

Recall What is the VTC output when

$V_{in} = 0$ exactly? NMOS cutoff, PMOS deep in triode: $V_{o u t} = V_{O H} \approx V_{D D}$ , with essentially zero static current flowing.

Recall What happens for

$V_{in}$ just below $V_{T n}$ ? Still region A — NMOS has not turned on yet, so no pull-down current exists and the output stays clamped at $V_{D D}$ ; the transition only begins once $V_{in}$ exceeds $V_{T n}$ .

Recall If the thresholds are so large that

$V_{T n} + ∣ V_{T p} ∣ > V_{D D}$ , what is odd about the VTC? There is an input band where neither transistor is on (both cutoff) — a dead-zone, meaning a stretch of $V_{in}$ over which no device biases into conduction. Without a defined pull the output holds its previous value — a degenerate, non-restoring inverter you must avoid by choosing thresholds below $V_{D D}$ .

Recall In the extreme

$r \to \infty$ (PMOS infinitely stronger than NMOS), where does $V_{M}$ go? The formula limits to $V_{M} \to V_{D D} - ∣ V_{T p} ∣$ — the switching point slides right up to just below the rail, because the overwhelming pull-up only surrenders when the NMOS is driven very hard.

Recall In the opposite extreme

$r \to 0$ (PMOS vanishingly weak), where does $V_{M}$ go? $V_{M} \to V_{T n}$ — the feeble pull-up gives way the instant the NMOS begins conducting, so the crossover sits at the NMOS threshold.

Recall What does the VTC of a symmetric inverter look like under reflection through its center?

It maps onto itself: rotating the curve $18 0^{\circ}$ about $(V_{D D} /2, V_{D D} /2)$ leaves it unchanged, which is the geometric statement of equal noise margins ( $N M_{H} = N M_{L}$ ).

Recall

Recall One-line antidotes to the top traps

$V_{M} = V_{D D} /2$ ⇒ only if $β_{n} = β_{p}$ AND equal thresholds.
Both saturated at $V_{M}$ ⇒ not one-on-one-off.
Steep ≠ floating ⇒ KCL pins $V_{o u t}$ .
Slope for noise margins ⇒ $- 1$ , use the magnitude.
Weak PMOS ⇒ widen it ( $W_{p} > W_{n}$ ) to center $V_{M}$ .

Connections

Voltage transfer characteristic (VTC) — parent topic these traps drill.
CMOS Inverter — the device under test.
MOSFET IV Characteristics — the triode/saturation regions each trap leans on.
Noise Margins — where the $- 1$ slope points feed in.
Short-circuit Power Dissipation — the region-C both-on cost.
Propagation Delay — the dynamic story the DC VTC deliberately omits.