Voltage transfer characteristic (VTC): Worked examples

Everything here uses only tools already built in Voltage transfer characteristic (VTC) and MOSFET IV Characteristics. Nothing new is assumed.

Definition

The five VTC regions, restated for this page. As $V_{in}$ climbs from $0$ to $V_{D D}$ , the pair of transistors passes through five operating regions, named by (NMOS state, PMOS state):

A — NMOS cutoff, PMOS triode → output pinned $\approx V_{D D}$ (flat top).
B — NMOS saturation, PMOS triode → output high, starting to drop.
C — both saturated (the transition region) → the near-vertical middle of the curve, where $∣ slope ∣ > 1$ .
D — NMOS triode, PMOS saturation → output low, still dropping.
E — NMOS triode, PMOS cutoff → output pinned $\approx 0$ (flat bottom).

The transition region is region C. It is steep precisely because both devices act as saturated current sources: a tiny $Δ V_{in}$ forces a large $Δ V_{o u t}$ to keep the currents balanced, so the magnitude of the slope exceeds $1$ .

The scenario matrix

Every VTC problem is one of these case classes. Each worked example below is tagged with the cell it fills.

Cell	Case class	What is unusual	Example
1	Balanced ( $r = 1$ , equal $V_{T}$ )	$V_{M}$ lands exactly at $V_{D D} /2$	Ex 1
2	Strong PMOS ( $r > 1$ )	$V_{M}$ pushed up toward $V_{D D}$	Ex 2
3	Weak PMOS ( $r < 1$ )	$V_{M}$ pulled down toward $0$	Ex 3
4	Design inverse problem	given target $V_{M}$ , solve for width ratio	Ex 4
5	Degenerate: threshold too high	a device is in cutoff where you expected it on	Ex 5
6	Limiting: $r \to \infty$ and $r \to 0$	infinitely strong / infinitely weak PMOS	Ex 6
7	Unequal thresholds ( $V_{T n} \neq = ∣ V_{T p} ∣$ )	asymmetry even when $r = 1$	Ex 7
8	Real-world word problem	mobility ratio → physical widths	Ex 8
9	Exam twist: sign trap	slope $= - 1$ vs $+ 1$ , magnitude of gain	Ex 9

The formula everyone below leans on (from the parent):

Figure — Voltage transfer characteristic (VTC)

The figure plots three full VTCs — output voltage $V_{o u t}$ (vertical axis) against input voltage $V_{in}$ (horizontal axis), both in volts. The magenta curve is a weak PMOS ( $r = 0.5$ ), the violet curve is the balanced inverter ( $r = 1$ ), and the orange curve is a strong PMOS ( $r = 1.5$ ). The dashed navy line is the 45° line $V_{o u t} = V_{in}$ ; where each colored curve crosses it is that inverter's switching threshold $V_{M}$ , marked with a labelled dot. Read the dots left-to-right: as the strength ratio $r$ grows (magenta → violet → orange), the crossing slides up and to the right, so a stronger pull-up raises $V_{M}$ . Each curve's steep middle stretch is its region C (the transition region). Keep this image in your head — every example below is just "which curve, and which dot?"

Cell 1 — the balanced inverter

Compute $r$ . $β_{n} = β_{p} \Rightarrow r = β_{p} / β_{n} = 1 = 1$ . Why this step? $r$ is the single knob in the $V_{M}$ formula; everything else is fixed voltages. Get it first.
Plug into the formula. $V_{M} = \frac{0.4 + 1 \cdot ( 1.8 - 0.4 )}{1 + 1} = \frac{0.4 + 1.4}{2} = \frac{1.8}{2} = 0.9 V .$ Why this step? Direct substitution — no algebra needed once $r$ is known.

Verify: $0.9 = V_{D D} /2$ exactly. That is the signature of a balanced inverter (equal noise margins). Units: volts throughout. ✓ Your forecast should have been $0.9 V$ .

Cell 2 — strong PMOS ( $r > 1$ )

Recall the direction rule. A stronger pull-up wins the tug-of-war until $V_{in}$ is fairly high, so $V_{M}$ should rise. Why this step? Predicting the sign of the shift catches arithmetic slips.
Substitute $r = 1.5$ . $V_{M} = \frac{0.4 + 1.5 ( 1.8 - 0.4 )}{1 + 1.5} = \frac{0.4 + 2.1}{2.5} = \frac{2.5}{2.5} = 1.0 V .$ Why this step? Same formula, new $r$ .

Verify: $1.0 > 0.9$ — moved up toward $V_{D D}$ , exactly as forecast for a strong PMOS. ✓

Cell 3 — weak PMOS ( $r < 1$ )

Substitute $r = 0.5$ . $V_{M} = \frac{0.4 + 0.5 ( 1.8 - 0.4 )}{1 + 0.5} = \frac{0.4 + 0.7}{1.5} = \frac{1.1}{1.5} = 0.7 \overline{3} V .$ Why this step? Only $r$ changed; reuse the formula.
Interpret. $0.733 < 0.9$ : the pull-down flips the output while $V_{in}$ is still low. Why this step? Ties the algebra back to the physical see-saw picture.

Verify: the three points from Cells 1–3 are monotone in $r$ : $r = 0.5 \to 0.733$ , $r = 1 \to 0.9$ , $r = 1.5 \to 1.0$ . Bigger $r$ ⇒ bigger $V_{M}$ , no reversals. ✓ (This is the ordering drawn in the figure.)

Cell 4 — the design inverse problem

Write the formula and cross-multiply. $V_{M} (1 + r) = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣) .$ Why this step? Clears the fraction so $r$ is no longer buried in a denominator.
Group the $r$ terms. $V_{M} + V_{M} r = V_{T n} + r (V_{D D} - ∣ V_{T p} ∣) \Rightarrow r [(V_{D D} - ∣ V_{T p} ∣) - V_{M}] = V_{M} - V_{T n} .$ Why this step? Collect everything containing $r$ on one side — the standard "solve for the unknown" move.
Isolate $r$ . $r = \frac{V _{M} - V _{T n}}{( V _{D D} - ∣ V _{T p} ∣) - V _{M}} = \frac{1.0 - 0.4}{( 1.8 - 0.4 ) - 1.0} = \frac{0.6}{0.4} = 1.5.$ Why this step? Divide off the bracket to leave $r$ alone.

Verify: matches Cell 2 ( $r = 1.5 \Rightarrow V_{M} = 1.0$ ). The formula and its inverse are consistent. ✓ Note the denominator $(V_{D D} - ∣ V_{T p} ∣) - V_{M}$ : if the target $V_{M}$ ever exceeds $V_{D D} - ∣ V_{T p} ∣$ , this goes negative — a warning we cash in at Cell 5.

Cell 5 — degenerate: a device stuck in cutoff

Try the inverse formula from Cell 4. $r = \frac{1.5 - 0.4}{( 1.8 - 0.4 ) - 1.5} = \frac{1.1}{- 0.1} = - 11.$ Why this step? Blindly applying the formula exposes the contradiction.
Read the impossible answer. $r = β_{p} / β_{n}$ is a ratio of square roots of positive quantities — it cannot be negative. So no finite sizing achieves $V_{M} = 1.5$ . Why this step? A negative $r$ is the algebra screaming that the physics is impossible.
Physical cause. At $V_{in} = 1.5 V$ the PMOS has $V_{S Gp} = V_{D D} - V_{in} = 0.3 V < ∣ V_{T p} ∣ = 0.4 V$ : the PMOS is in cutoff. A transistor that is off carries no current, so it cannot balance the NMOS. This violates the operating-region assumption stated at the top — the $V_{M}$ formula only holds when both devices are saturated (region C), and here the PMOS has left saturation entirely. Why this step? Explains which modelling assumption fails, not just that it fails.

Verify: The ceiling for a valid $V_{M}$ is $V_{D D} - ∣ V_{T p} ∣ = 1.4 V$ (PMOS still on) and the floor is $V_{T n} = 0.4 V$ (NMOS still on). $1.5 > 1.4$ , so it is out of range — the negative $r$ is the correct diagnosis. ✓

Cell 6 — limiting behaviour $r \to \infty$ and $r \to 0$

Limit $r \to \infty$ . Divide top and bottom of the formula by $r$ : $V_{M} = \frac{\frac{V _{T n}}{r} + ( V _{D D} - ∣ V _{T p} ∣)}{\frac{1}{r} + 1} r \to \infty V_{D D} - ∣ V_{T p} ∣ = 1.4 V .$ Why this step? Dividing by $r$ isolates the dominant term; the $1/ r$ pieces vanish. This is exactly the ceiling from Cell 5.
Limit $r \to 0$ . Set $r = 0$ directly: $V_{M} \to \frac{V _{T n} + 0}{1 + 0} = V_{T n} = 0.4 V .$ Why this step? At $r = 0$ the PMOS terms drop out, leaving the NMOS threshold — the floor from Cell 5.

Verify: the two limits $1.4$ V and $0.4$ V are precisely the valid-range endpoints found in Cell 5. Every achievable $V_{M}$ lives in the open interval $(0.4, 1.4)$ V, and the finite examples (0.733, 0.9, 1.0) all sit inside it. ✓

Cell 7 — unequal thresholds, still $r = 1$

Substitute $r = 1$ . $V_{M} = \frac{V _{T n} + ( V _{D D} - ∣ V _{T p} ∣)}{2} = \frac{0.5 + ( 1.8 - 0.3 )}{2} = \frac{0.5 + 1.5}{2} = \frac{2.0}{2} = 1.0 V .$ Why this step? With $r = 1$ the formula collapses to a simple average — but of $V_{T n}$ and $V_{D D} - ∣ V_{T p} ∣$ , not of $0$ and $V_{D D}$ .
Interpret the shift. The NMOS needs more input to turn on (higher $V_{T n}$ ) and the PMOS turns off easily (lower $∣ V_{T p} ∣$ ), so both effects nudge $V_{M}$ up. Why this step? Distinguishes "balanced strengths" from "balanced thresholds" — two different symmetries.

Verify: $1.0 \neq = 0.9$ , so $r = 1$ alone does not guarantee $V_{M} = V_{D D} /2$ ; you also need $V_{T n} = ∣ V_{T p} ∣$ . Consistent with the parent's mistake box. ✓

Cell 8 — real-world word problem (mobility → widths)

Write the balance condition. $r = 1 \Leftrightarrow β_{p} = β_{n} \Leftrightarrow k_{p}^{'} \frac{W _{p}}{L} = k_{n}^{'} \frac{W _{n}}{L} .$ Why this step? $r = 1$ is the definition of "balanced"; unpack it into device parameters.
Cancel $L$ and solve for $W_{p}$ . $W_{p} = \frac{k _{n}^{'}}{k _{p}^{'}} W_{n} = \frac{270}{90} \cdot 1 μ m = 3 μ m .$ Why this step? $L$ is common; the width ratio must undo the mobility ratio.
Confirm $V_{M}$ . With $r = 1$ , $V_{T n} = ∣ V_{T p} ∣ = 0.4$ : $V_{M} = \frac{0.4 + ( 1.8 - 0.4 )}{2} = 0.9 V = V_{D D} /2$ . Why this step? Closes the loop — the sizing achieves the intended centered threshold.

Verify: $W_{p} / W_{n} = 3$ equals $k_{n}^{'} / k_{p}^{'} = 3$ (the mobility handicap exactly compensated), and $V_{M} = 0.9 = V_{D D} /2$ . Units: $μ A/V^{2}$ cancels in the ratio, leaving pure $μ m$ . ✓ This is why real layouts draw PMOS 2–3× wider — see Static CMOS Logic Gates.

Cell 9 — exam twist: the sign trap

Before we start, two reminders used below.

(a) Transition region test. Region C is where $∣ slope ∣ > 1$ . $∣ - 4 ∣ = 4 > 1$ , $∣ - \frac{1}{2} ∣ = \frac{1}{2} < 1$ . So slope $= - 4$ is inside the steep transition region C. Why this step? High gain magnitude is the fingerprint of both devices saturated.
(b) Unity-gain point. $V_{I L}, V_{I H}$ are defined by $\frac{d V _{o u t}}{d V _{in}} = - 1$ . Neither given point is exactly $- 1$ , but the $- \frac{1}{2}$ point (magnitude below 1) lies outside region C, on the flat approach to a rail — so a unity-gain point sits between the two points, where the slope passes through $- 1$ . Why this step? Locates $V_{I L} / V_{I H}$ as the crossover between "amplify noise" and "reject noise."
(c) Why $+ 1$ finds nothing. The inverter inverts: as $V_{in}$ rises, $V_{o u t}$ falls, so $d V_{o u t} / d V_{in} < 0$ everywhere on the curve. A search for $+ 1$ scans only positive slopes, which never occur. Why this step? Exposes the classic sign mistake — use magnitude $1$ , condition $- 1$ .

Verify: condition is $\frac{d V _{o u t}}{d V _{in}} = - 1$ (magnitude $1$ , sign negative). $- 4$ has magnitude $4 > 1$ (region C, high gain, short-circuit current — see Short-circuit Power Dissipation); $- \frac{1}{2}$ has magnitude $< 1$ (noise-rejecting flat region). No positive slope exists. ✓ Details of margins live in Noise Margins.

Active recall

Recall Which cell am I in? (hidden)

Given $r = 1.5$ , $V_{D D} = 1.8$ , equal $V_{T} = 0.4$ , what is $V_{M}$ ? ::: $1.0$ V (Cell 2, strong PMOS).
Given weak PMOS $r = 0.5$ (same voltages), what is $V_{M}$ ? ::: $0.7 \overline{3}$ V (Cell 3).
What is the valid range of achievable $V_{M}$ here? ::: $(V_{T n}, V_{D D} - ∣ V_{T p} ∣) = (0.4, 1.4)$ V (Cells 5–6).
$r = 1$ but $V_{T n} = 0.5, ∣ V_{T p} ∣ = 0.3$ : is $V_{M} = V_{D D} /2$ ? ::: No, $V_{M} = 1.0$ V (Cell 7 — need equal thresholds too).
Mobility ratio $k_{n}^{'} / k_{p}^{'} = 3$ : PMOS width for balance? ::: $W_{p} = 3 W_{n}$ (Cell 8).
Which region is the steep, both-saturated transition? ::: Region C, bordered by the unity-gain points $V_{I L}, V_{I H}$ (Cell 9).

Connections

Voltage transfer characteristic (VTC) — the parent this page drills.
CMOS Inverter — the device under test.
MOSFET IV Characteristics — square-law currents behind $V_{M}$ .
Noise Margins — the $- 1$ slope points from Cell 9.
Static CMOS Logic Gates — why PMOS is drawn wider (Cell 8).
Short-circuit Power Dissipation — the crowbar current of region C (Cell 9).
Propagation Delay — strength ratio $r$ also sets rise/fall timing.