Voltage transfer characteristic (VTC) — Hinglish notes

3.2.5 · Hardware › CMOS Circuit Design

WHAT is the VTC?

Jo defining physical constraint hai woh hai Kirchhoff's Current Law output node par:

$I_{D N} = I_{D P}$

NMOS drain current (neeche pull karna) ko PMOS drain current (upar pull karna) ke barabar hona chahiye, kyunki steady state mein koi net current output node ko charge nahi karti.

HOW the transistors take turns (5 regions)

Define karo, NMOS ke liye: $V_{GS n} = V_{in}$ , $V_{D S n} = V_{o u t}$ , threshold $V_{T n} > 0$ . PMOS ke liye: $V_{S Gp} = V_{D D} - V_{in}$ , $V_{S D p} = V_{D D} - V_{o u t}$ , threshold $∣ V_{T p} ∣$ .

Har transistor cutoff / saturation / triode mein ho sakta hai:

Region	$V_{in}$ range	NMOS	PMOS	$V_{o u t}$
A	$0 \leq V_{in} < V_{T n}$	cutoff	triode	$\approx V_{D D}$
B	badhta hua	saturation	triode	high, girta hua
C	$V_{M}$ ke paas	saturation	saturation	steep drop
D	badhta hua	triode	saturation	low, girta hua
E	$V_{in}>V_{DD}-	V_{Tp}	$	triode

Figure — Voltage transfer characteristic (VTC)

DERIVATION: the switching threshold $V_{M}$

Har step kyun?

$V_{M}$ par dono saturated hain → kyunki $V_{in} = V_{o u t}$ ka matlab hai $V_{D S n} = V_{o u t} > V_{in} - V_{T n} = V_{GS n} - V_{T n}$ ; saturation inequality hold karta hai. → square-law equations use karo.
Currents equal set karo → output par KCL (defining constraint).
Square roots lo → dono sides perfect squares hain; lena $V_{M}$ mein linearize kar deta hai. $β_{n} (V_{M} - V_{T n}) = β_{p} (V_{D D} - V_{M} - ∣ V_{T p} ∣)$
$β_{n}$ se divide karo, $V_{M}$ collect karo → boxed formula milta hai.

Noise margins from the VTC

Common mistakes (steel-manned)

Active recall

Recall Test yourself (hidden)

VTC ka har point kaunsi constraint define karta hai? ⇒ $I_{D N} = I_{D P}$ (KCL).
Kis region mein DONO transistors saturated hote hain? ⇒ transition region (C), $V_{M}$ par/ke paas.
$V_{M}$ ko $V_{D D}$ ki taraf upar kya shift karta hai? ⇒ stronger PMOS (bada $r = β_{p} / β_{n}$ ).
$V_{I L}, V_{I H}$ define karo. ⇒ woh points jahan slope $= - 1$ ho.

Recall Feynman: explain to a 12-year-old

Socho ek see-saw hai jisme ek taraf "0-kid" aur doosri taraf "1-kid" hai, dono output ko push kar rahe hain. Tum ek lever (input) ko left se right slide karte ho. Pehle 1-kid bilkul jeet jaata hai aur output HIGH pe stuck rehta hai. Jaise-jaise tum slide karte ho, 0-kid stronger hota jaata hai, aur ek special jagah par dono exactly tie ho jaate hain — ek tiny sa dhakka output ko HIGH se LOW super fast tip kar deta hai. Woh fast tipping hi reason hai ki computers ek clean "1" ko ek clean "0" se tab bhi pehchaan lete hain jab wire thoda noisy ho. Dono kids ko equally strong banana tipping point ko exactly beech mein rakhta hai — sabse fair aur safe jagah.

Flashcards

CMOS inverter VTC ke har point par kaunsi DC constraint hold karti hai?

I_{D N} = I_{D P}

(KCL: series transistors, output cap fully charged).

V_{M}

par simultaneously kaun si do device states hoti hain?

NMOS aur PMOS dono saturation mein.

r = β_{p} / β_{n}

ke saath switching threshold

V_{M}

ka formula?

V_{M} = \frac{V _{T n} + r ( V _{D D} - ∣ V _{T p} ∣ )}{1 + r}

Symmetric inverter ke liye

r

par kya condition hoti hai (

V_{M} = V_{D D} /2

, equal

V_{T}

r = 1

, matlab

β_{n} = β_{p}

Centered

V_{M}

ke liye

W_{p} > W_{n}

kyun hona chahiye?

Hole mobility < electron mobility (

k_{p}^{'} < k_{n}^{'}

), toh PMOS width ko strength equal karne ke liye badhana padta hai.

VTC par

V_{I L}

aur

V_{I H}

kaise define hote hain?

Woh points jahan

d V_{o u t} / d V_{in} = - 1

ho (unity-gain points).

VTC levels ke terms mein noise margins?

N M_{H} = V_{O H} - V_{I H}

N M_{L} = V_{I L} - V_{O L}

Agar PMOS ko stronger banaya jaaye (r badhta hai) toh

V_{M}

ka kya hoga?

V_{M}

badh jaata hai (

V_{D D}

ki taraf move karta hai).

Transition region itna steep kyun hota hai?

Dono devices saturated current sources ki tarah kaam karte hain; chhota

Δ V_{in}

currents equal rakhne ke liye bada

Δ V_{o u t}

maangta hai → high gain.

Transition region mein operate karne ki extra cost kya hai?

Short-circuit (crowbar) current, kyunki dono transistors simultaneously conduct karte hain.

Connections

CMOS Inverter — woh device jiska VTC yeh hai.
MOSFET IV Characteristics — triode/saturation square-law equations jo derivation mein use hui hain.
Noise Margins — $V_{I L}, V_{I H}, V_{O H}, V_{O L}$ se compute hote hain.
Static CMOS Logic Gates — VTC effective W/L ke zariye NAND/NOR tak generalize hoti hai.
Short-circuit Power Dissipation — both-ON transition region se aati hai.
Propagation Delay — slope/gain switching speed se relate karta hai.