Question bank — Static vs dynamic power dissipation

False — a full charge+discharge dissipates $C_L{V}_{DD}^2$ regardless of $R$; smaller $R$ just charges faster (shorter time constant), and the larger current is exactly cancelled by the shorter duration.

True — energy per cycle ($C_L{V}_{DD}^2$) is fixed, and $P=\alpha C_L{V}_{DD}^{2}f$ is linear in $f$, so twice the cycles per second means twice the power.

False — it quadruples it, because $P\propto V_{DD}^2$: one factor from the charge $Q=CV$ and one from the voltage that charge is pushed through.

True — leakage (subthreshold, gate-tunnel, junction) is present whenever the chip is powered, independent of any switching activity.

True in the ideal limit — $t_{sc}$ is proportional to the input transition time, so a zero-width edge gives no window where both transistors conduct.

True — subthreshold current $\propto e^{(V_{GS}-V_T)/(n{V}_{th})}$, so raising $V_T$ pushes the exponent more negative and cuts leakage exponentially (at the cost of slower gates).

False — this confuses energy with power; energy per cycle is fixed, but power is energy times cycles-per-second, so all of switching power scales with $f$.

False — the supply delivers $C_L{V}_{DD}^2$ but only $\frac{1}{2}{C}_L{V}_{DD}^2$ ends up stored; the other half is dissipated as heat in the PMOS during charging.

False — $\alpha$ is a probability (fraction of clock cycles with a rising transition), so it lives in $[0,1]$; a node toggling every cycle has $\alpha =1$ at most for rising edges.

False — it slashes dynamic power but slows gates (Propagation delay in CMOS rises), possibly forcing higher $f$ or extra stages, and it shifts the leakage/timing trade-off; it is an optimization, not a free lunch.

Wrong — during discharge the supply is disconnected from the output; the energy burned is the $\frac{1}{2}{C}_L{V}_{DD}^2$ that was stored on the capacitor, now dumped to ground through the NMOS.

Wrong direction — $t_{sc}$ grows with slower edges, so slow inputs widen the crowbar window and increase short-circuit power; sharp edges reduce it.

Wrong — static power is $I_{leak}{V}_{DD}$ (a simple current-times-voltage), linear in $V_{DD}$; only switching power carries the $V_{DD}^2$ because of the separate charge and push-through factors.

Wrong — raising $f$ increases dynamic power but does nothing to reduce the always-on leakage current; you would burn more total power, not less.

Wrong — with zero activity there are no transitions, so $P_{switching}=\alpha C_L{V}_{DD}^{2}f=0$; only leakage (static) remains despite the running clock.

Wrong — short-circuit current only flows during input transitions and scales with $\alpha f$, making it dynamic; static leakage flows with the input held steady and no switching.

Because the integral of $I^{2}R$ over the charging transient always evaluates to $\frac{1}{2}{C}_L{V}_{DD}^2$; a larger $R$ gives smaller current but for proportionally longer, and the two effects cancel exactly.

The quadratic dependence $P\propto V_{DD}^2$ means a modest voltage cut gives a squared payoff — halving $V_{DD}$ cuts switching power by 4×, far more than any linear knob like $\alpha$ or $f$. See Voltage scaling and Dennard scaling.

Chasing speed required lowering $V_T$ alongside $V_{DD}$, but subthreshold current rises exponentially as $V_T$ falls, so a linear scaling of $V_T$ produced a runaway growth in static power. See Threshold voltage and subthreshold conduction.

Clock gating stops the clock to a block, killing its switching activity ($\alpha f\to 0$) but leakage remains; power gating physically disconnects $V_{DD}$, removing the leakage path entirely. See Power gating and clock gating.

Switching energy is capacitive ($E=C{V}^2$), inherently quadratic; short-circuit power is a transient conduction current times $V_{DD}$, roughly linear in $V_{DD}$ apart from how the conduction window shifts with voltage.

$C_L$ in $\alpha C_L{V}_{DD}^{2}f$ includes wire capacitance, and as wires got long and dense relative to shrinking gates, interconnect became a large share of the switched load. See Capacitance in interconnects.

Even with steady inputs, subthreshold, gate-tunnel, and junction leakage currents flow continuously, giving $P_{static}=I_{leak}{V}_{DD}>0$.

Only static leakage — $P_{static}=I_{leak}{V}_{DD}$; both switching and short-circuit terms are zero because they need transitions.

The exponent $(V_{GS}-V_T)/(n{V}_{th})$ climbs, so leakage grows without a hard bound and the "off" transistor conducts nearly like an "on" device — the failure mode of aggressive $V_T$ scaling.

Static leakage grows, because the thermal voltage $V_{th}=kT/q$ increases with $T$ and subthreshold current depends exponentially on it, so hotter chips leak more — a positive-feedback thermal risk.

Zero switching power ($\alpha C_L{V}_{DD}^{2}f=0$), but short-circuit and static power can still be nonzero, so total power does not vanish.

Gate delay $\propto V_{DD}/(V_{DD}-V_T{)}^2$ blows up as $V_{DD}\to V_T$, so the gate becomes unusably slow even though dynamic power is tiny — the practical floor on voltage scaling. See Propagation delay in CMOS.

Static leakage during sleep, unless the idle blocks are power-gated; this is exactly why phones aggressively disconnect idle domains rather than merely clock-gate them.