The parent note gave you two clean formulas:
P switching = α C L V D D 2 f , P static = I leak V D D
But formulas only stick when you've dragged them through every corner case — big and small, zero and extreme, textbook and real-world. This page is a grid: we list every kind of situation the topic can throw, then solve one example per box so you never meet a scenario you haven't already seen.
Prerequisites we lean on: CMOS Inverter operation , Threshold voltage and subthreshold conduction , Voltage scaling and Dennard scaling , Power gating and clock gating , Capacitance in interconnects . Parent: Static vs dynamic power (topic) .
Before solving anything, let's map the whole territory. Each cell is a class of problem this topic can generate. Every worked example below is tagged with the cell it fills.
Cell
What makes it distinct
Filled by
A. Plain plug-in
All four dynamic quantities given, just substitute
Ex 1
B. Scaling knob
One variable changes (V D D , f , α ) — predict the ratio
Ex 2
C. Degenerate / zero input
α = 0 (idle), or f = 0 — what survives?
Ex 3
D. Static leakage aggregation
Nanoamps × millions of gates → watts
Ex 4
E. Crossover point
Where does static equal dynamic? Solve for the boundary
Ex 5
F. Limiting behaviour
Exponential leakage as V T → small; what dominates
Ex 6
G. Real-world word problem
Battery life of a phone block
Ex 7
H. Exam twist
Trap that mixes energy-vs-power, or resistance
Ex 8
Intuition Why this grid and not a list?
A list of examples can accidentally repeat the same kind of thinking eight times. A grid forces us to hit each independent behaviour — linear knobs, quadratic knobs, exponential knobs, zero limits, and the two words-into-math traps that exams love.
Worked example Example 1 — Dynamic power of a logic block
An adder toggles with α = 0.15 , drives C L = 2 pF , runs at V D D = 1.2 V , clock f = 1 GHz . Find P switching .
Forecast: picofarads and gigahertz look tiny and huge — guess whether the answer lands in microwatts or milliwatts before reading on.
Write the formula. P = α C L V D D 2 f .
Why this step? Every dynamic-switching problem starts here; we're just filling four slots.
Substitute numbers with their powers of ten.
P = 0.15 × ( 2 × 1 0 − 12 ) × ( 1.2 ) 2 × ( 1 × 1 0 9 )
Why this step? Keeping powers of ten separate stops arithmetic slips.
Group the constants: 0.15 × 2 × 1.44 = 0.432 , and the powers 1 0 − 12 × 1 0 9 = 1 0 − 3 .
Why this step? Do the "nice" numbers and the "scale" numbers separately.
Combine: P = 0.432 × 1 0 − 3 W = 0.432 mW .
Verify: Units — F ⋅ V 2 ⋅ Hz = ( C/V ) ⋅ V 2 ⋅ ( 1/ s ) = C ⋅ V / s = J/s = W . ✓ Landed in milliwatts , matching intuition (bigger cap and voltage than the parent's Example 1).
Worked example Example 2 — Three knobs turned at once
Starting from Example 1, an engineer doubles α , halves V D D , and triples f . By what factor does P switching change?
Forecast: guess the net factor. Many people say "2 × 2 1 × 3 = 3 × " — is that right?
Identify how each knob enters. α is linear, V D D is squared , f is linear.
Why this step? The exponent decides how a change propagates — the whole trap lives here.
Turn each change into a multiplier.
α : × 2
V D D : halved, but squared ⇒ ( 2 1 ) 2 = × 4 1
f : × 3
Why this step? Halving the voltage is not halving the power ; the square bites here.
Multiply the factors: 2 × 4 1 × 3 = 4 6 = 1.5 .
Why this step? Power is a product of these terms, so ratios of terms just multiply.
State the result: new power is 1.5 × the old, i.e. 0.432 mW × 1.5 = 0.648 mW .
Verify: Recompute from scratch: α = 0.3 , V D D = 0.6 , f = 3 × 1 0 9 . P = 0.3 × 2 × 1 0 − 12 × 0.36 × 3 × 1 0 9 = 0.648 mW . ✓ The naive "3 × " answer was wrong because it forgot to square the voltage change.
Look at the chalkboard bars: the pale-yellow V D D 2 term shrinks four-fold while the linear knobs push the other way — the net is a modest 1.5 × , not the 3 × you'd guess by treating voltage linearly.
Worked example Example 3 — The idle chip (what survives when nothing switches?)
A block sits idle : activity α = 0 (no node toggles), but the power is still on, V D D = 1.0 V , and each of its 5 × 1 0 6 gates leaks I leak = 20 nA . What total power does it draw?
Forecast: with α = 0 , is the power exactly zero?
Kill the dynamic term. P switching = α C L V D D 2 f with α = 0 gives P switching = 0 .
Why this step? Dynamic power is paid only when the output changes — no change, no charge sloshing, no cost.
Short-circuit term also vanishes. P sc ≈ α f I ˉ sc V D D t sc also has α = 0 ⇒ 0 .
Why this step? Crowbar current only flows during transitions ; idle means no transitions.
Only leakage remains. Total leakage current I = 5 × 1 0 6 × 20 × 1 0 − 9 = 0.1 A .
Why this step? Leakage flows always , independent of switching — this is the whole point of "static".
Compute static power: P static = I V D D = 0.1 × 1.0 = 0.1 W = 100 mW .
Verify: Sanity — an idle block drawing 100 mW is exactly why designers add power gating to cut V D D off entirely. If we had also set V D D = 0 (true power-off), even leakage would vanish since P static = I leak V D D → 0 . ✓ "Idle" is not "zero power".
Worked example Example 4 — Nanoamps become watts
A chip has 2 × 1 0 8 gates, each leaking I leak = 5 nA , at V D D = 0.9 V . Find static power.
Forecast: five nanoamps sounds negligible. Guess the total in watts.
Total leakage current = N × I leak = 2 × 1 0 8 × 5 × 1 0 − 9 .
Why this step? Leakage paths are in parallel, so their currents simply add.
Evaluate: 2 × 1 0 8 × 5 × 1 0 − 9 = 1 0 0 = 1 A .
Why this step? 1 0 8 × 1 0 − 9 = 1 0 − 1 , times 2 × 5 = 10 , gives 1 .
Multiply by supply: P static = 1 A × 0.9 V = 0.9 W .
Why this step? P = I V — leakage current dropped across the full supply.
Verify: Units A·V = W ✓. Nearly a watt from "negligible" nanoamps — the multiplier is the 2 × 1 0 8 gate count. This is the core message of subthreshold leakage scaling.
Worked example Example 5 — Where does static equal dynamic?
A gate has C L = 1.5 pF , V D D = 1.0 V , α = 0.1 , and leaks I leak = 8 nA . Below what clock frequency does static power exceed dynamic ?
Forecast: below or above ~1 GHz? Guess first.
Set the two powers equal at the boundary.
α C L V D D 2 f = I leak V D D
Why this step? The crossover is by definition where dynamic = static; solving the equation finds that frequency.
Cancel one V D D and solve for f .
f = α C L V D D I leak
Why this step? Divide both sides by α C L V D D 2 ; one V D D survives in the denominator.
Substitute: f = 0.1 × 1.5 × 1 0 − 12 × 1.0 8 × 1 0 − 9 .
Why this step? Every symbol now has a number; just plug in.
Evaluate: denominator = 0.15 × 1 0 − 12 = 1.5 × 1 0 − 13 ; so f = 1.5 × 1 0 − 13 8 × 1 0 − 9 ≈ 5.33 × 1 0 4 Hz ≈ 53.3 kHz .
Verify: Below ≈ 53 kHz , static wins; above it, dynamic wins. Sanity check by plugging f = 53.3 kHz back: dynamic = 0.1 × 1.5 × 1 0 − 12 × 1 × 5.33 × 1 0 4 = 8 × 1 0 − 9 W ; static = 8 × 1 0 − 9 × 1.0 = 8 × 1 0 − 9 W . Equal ✓. A high-performance chip at GHz is deep in dynamic-dominated territory; a sleepy sensor at kHz is leakage-dominated.
The crossing point on the chalkboard plot is where the rising blue dynamic line meets the flat pink static line — everything left of it is a leakage problem, everything right is a switching problem.
Worked example Example 6 — Dropping the threshold voltage
Subthreshold leakage follows I s u b ∝ e − V T / ( n V t h ) with n = 1.5 and thermal voltage V t h = 26 mV at 300 K. A design lowers V T from 0.35 V to 0.25 V for speed. By what factor does leakage grow?
Forecast: dropping V T by 0.1 V — does leakage roughly double, or explode by an order of magnitude?
Take the ratio of the two leakages. The proportionality constant cancels:
I s u b old I s u b new = e − V T old / ( n V t h ) e − V T new / ( n V t h ) = e ( V T old − V T new ) / ( n V t h )
Why this step? We don't know the constant, but ratios erase it — leaving only the change in V T .
Insert the numbers into the exponent.
n V t h Δ V T = 1.5 × 0.026 0.35 − 0.25 = 0.039 0.10 ≈ 2.564
Why this step? The exponential's argument is the only thing that matters; compute it carefully.
Exponentiate: ratio = e 2.564 ≈ 12.99 .
Why this step? e 2.564 turns the linear voltage drop into a multiplicative blow-up.
Verify: A mere 100 mV cut in V T multiplied leakage by about 13 × . This exponential sensitivity (not linear!) is exactly why aggressive threshold scaling made static power a monster. Limit check: as V T → 0 , the exponent → (positive, large) and I s u b → huge — the transistor stops being a good "off" switch. ✓
Worked example Example 7 — Phone screen driver, battery budget
A display block draws P active = 180 mW while animating (10% of the day) and P idle = 20 mW leakage the rest of the time (90%). The battery holds 10 Wh . If this block were the only load, how many hours until empty?
Forecast: closer to 50 h or 250 h? Guess.
Average the power over a day (weighted by time fraction).
P avg = 0.10 × 180 + 0.90 × 20 [ mW ]
Why this step? Energy = power × time; over a mixed day the time-weighted average power sets the drain.
Compute: 0.10 × 180 = 18 , 0.90 × 20 = 18 , sum = 36 mW = 0.036 W .
Why this step? Notice leakage (idle) contributes as much as the active bursts — the takeaway.
Battery life = power energy = 0.036 W 10 Wh .
Why this step? Watt-hours ÷ watts = hours; the units cancel cleanly.
Evaluate: 10/0.036 ≈ 277.8 h .
Verify: ≈ 278 hours. Units: Wh / W = h ✓. Note the punchline — half the drain is idle leakage , so power-gating the idle state to near-zero would roughly halve P avg and nearly double battery life.
Worked example Example 8 — The resistance trap
A cap C L = 0.5 pF charges to V D D = 1.0 V then discharges, once. (a) How much energy is dissipated as heat over the full up-then-down cycle? (b) If the PMOS on-resistance were doubled, how does that heat change?
Forecast: most students think doubling R doubles the heat. True or false?
Energy dissipated charging = 2 1 C L V D D 2 (half the supply energy; the other half is stored on the cap).
Why this step? From the parent derivation — the "½ each way" magic.
Energy dissipated discharging = 2 1 C L V D D 2 (the stored half is now dumped through the NMOS).
Why this step? Discharge burns exactly what charge stored.
Full-cycle heat = 2 1 C L V D D 2 + 2 1 C L V D D 2 = C L V D D 2 .
= 0.5 × 1 0 − 12 × ( 1.0 ) 2 = 5 × 1 0 − 13 J = 0.5 pJ
Why this step? The two halves add to the full supply energy per cycle.
(b) Effect of doubling R : none. Total heat = C L V D D 2 contains no R .
Why this step? Bigger R means smaller current for longer time; the product ∫ i 2 R d t stays 2 1 C L V D D 2 . R sets speed (the time constant τ = R C ), not energy .
Verify: Full-cycle heat = 0.5 pJ , independent of R ✓. The trap ("double R → double heat") confuses instantaneous power I 2 R with total energy ; over the transient, current falls exactly enough to cancel the larger R . This matches [!mistake] #1 in the parent note.
Recall Quick self-test across the matrix
With α = 0 , what power remains? ::: Only static (leakage) P static = I leak V D D ; both dynamic terms vanish.
Halving V D D changes switching power by what factor? ::: × 4 1 (quadratic in V D D ).
5 nA leakage across 2 × 1 0 8 gates at 0.9 V gives? ::: 0.9 W .
Crossover frequency formula (static = dynamic)? ::: f = I leak / ( α C L V D D ) .
Dropping V T by 0.1 V (n = 1.5 , V t h = 26 mV ) multiplies leakage by about? ::: ≈ 13 × (exponential).
Does doubling transistor R change per-cycle switching energy? ::: No — energy is C L V D D 2 , R only sets speed.