Static vs dynamic power dissipation: Exercises — Hardware deep dive

The two anchor formulas we will lean on the whole way:

Related ideas you may want open in another tab: CMOS Inverter operation, Threshold voltage and subthreshold conduction, Voltage scaling and Dennard scaling, Power gating and clock gating, Propagation delay in CMOS, Capacitance in interconnects.

Level 1 — Recognition

You just need to pick the right formula and read off a number.

L1.1

A node has $C_{L} = 2 pF$ , $V_{D D} = 1.2 V$ , $f = 1 GHz$ , and it toggles on every clock (so $α = 1$ ). Find its switching power.

Recall Solution

WHAT we need: switching power, so use $P = α C_{L} V_{D D}^{2} f$ . WHY this formula: it toggles every clock (dynamic, capacitive), nothing is idle. $P = 1 \times (2 \times 1 0^{- 12}) \times (1.2)^{2} \times (1 \times 1 0^{9})$ $= 2 \times 1 0^{- 12} \times 1.44 \times 1 0^{9} = 2.88 \times 1 0^{- 3} W = 2.88 mW$ Answer: $2.88 mW$ .

L1.2

A chip is fully idle (clock stopped, nothing switching) but still draws $I_{leak} = 200 mA$ at $V_{D D} = 0.9 V$ . Is this dynamic or static power, and how much is it?

Recall Solution

WHAT/WHY: the clock is stopped, so $f$ -dependent dynamic power is zero. Current that flows while idle is leakage → static power. Use $P_{static} = I_{leak} V_{D D}$ . $P_{static} = 0.2 A \times 0.9 V = 0.18 W$ Answer: static power, $0.18 W$ .

Level 2 — Application

Now plug into the formulas with a small twist (unit conversions, one algebra step).

L2.1

A bus has $C_{L} = 500 fF$ , runs at $V_{D D} = 1.0 V$ , $f = 3 GHz$ , activity $α = 0.15$ . Compute switching power.

Recall Solution

WHAT we need: switching power of a toggling bus, so use $P = α C_{L} V_{D D}^{2} f$ . WHY this formula: the bus is actively switching (dynamic, capacitive), and we are given exactly the four inputs $α, C_{L}, V_{D D}, f$ that formula asks for — no leakage or resistance is involved. First convert: $500 fF = 500 \times 1 0^{- 15} F = 5 \times 1 0^{- 13} F$ . $P = 0.15 \times 5 \times 1 0^{- 13} \times (1.0)^{2} \times 3 \times 1 0^{9}$ $= 0.15 \times 5 \times 1 0^{- 13} \times 3 \times 1 0^{9} = 0.15 \times 1.5 \times 1 0^{- 3} = 2.25 \times 1 0^{- 4} W$ Answer: $0.225 mW$ .

L2.2

A gate dissipates $\frac{1}{2} C_{L} V_{D D}^{2}$ of heat each time it charges $C_{L}$ . With $C_{L} = 1 pF$ and $V_{D D} = 1.5 V$ , how much heat is burned in the PMOS on one rising edge, and how much total per full up-then-down cycle?

Recall Solution

WHY split it: on the rising edge the supply spends $C_{L} V_{D D}^{2}$ ; half is stored on the cap, half ( $\frac{1}{2} C_{L} V_{D D}^{2}$ ) is burned in the PMOS resistance. On the falling edge the stored half is dumped through the NMOS as heat. So per full cycle the total heat is $C_{L} V_{D D}^{2}$ (parent §2 "magic ½ each way"). $E_{PMOS, rise} = \frac{1}{2} C_{L} V_{D D}^{2} = \frac{1}{2} (1 \times 1 0^{- 12}) (1.5)^{2} = \frac{1}{2} (2.25 \times 1 0^{- 12}) = 1.125 \times 1 0^{- 12} J$ $E_{cycle} = C_{L} V_{D D}^{2} = 2.25 \times 1 0^{- 12} J$ Answers: $1.125 pJ$ on the rising edge; $2.25 pJ$ per full cycle.

L2.3

A block has $1 0^{6}$ gates, each leaking $I = 20 nA$ at $V_{D D} = 0.8 V$ . Total static power?

Recall Solution

Total leakage current: $I_{leak} = 1 0^{6} \times 20 \times 1 0^{- 9} A = 2 \times 1 0^{- 2} A = 20 mA$ . $P_{static} = 20 \times 1 0^{- 3} \times 0.8 = 1.6 \times 1 0^{- 2} W = 16 mW$ Answer: $16 mW$ . (Nanoamps × a million gates = real milliwatts — see Power gating and clock gating.)

Level 3 — Analysis

Here you compare, take ratios, and reason about why a quantity moves.

L3.1

A design keeps everything fixed but scales $V_{D D}$ from $1.2 V$ down to $0.8 V$ . By what factor does switching power change? (Assume $α, C_{L}, f$ unchanged.)

Recall Solution

Switching power is $\propto V_{D D}^{2}$ , so the ratio is $(0.8/1.2)^{2}$ . $\frac{P _{new}}{P _{old}} = (\frac{0.8}{1.2})^{2} = (\frac{2}{3})^{2} = \frac{4}{9} \approx 0.444$ Answer: switching power drops to $\frac{4}{9} \approx 44.4%$ of the original (a ~55.6% saving). The quadratic $V_{D D}^{2}$ makes voltage the strongest lever — see Voltage scaling and Dennard scaling.

L3.2

A node's total power is $P_{total} = P_{switching} + P_{static}$ . Measurements: at $f = 1 GHz$ , $P_{total} = 5 mW$ ; at $f = 2 GHz$ (same $V_{D D}$ , same activity), $P_{total} = 9 mW$ . Separate the switching and static parts.

Recall Solution

WHY this works: switching power is linear in $f$ while static is independent of $f$ . So plot power vs frequency — it's a straight line whose slope is the switching coefficient and whose intercept is the static floor.

Let $P_{switching} = k f$ and $P_{static} = S$ (constant). Then: $k (1) + S = 5, k (2) + S = 9$ Subtract: $k (2 - 1) = 9 - 5 \Rightarrow k = 4 mW per GHz$ . Back-substitute: $S = 5 - 4 (1) = 1 mW$ .

At $1 GHz$ : switching $= 4 mW$ , static $= 1 mW$ .
At $2 GHz$ : switching $= 8 mW$ , static $= 1 mW$ .

The figure below plots the two measured points (red) and the straight line through them. Read it geometrically: the line's slope ( $4 mW$ per GHz, orange) is the switching coefficient $k$ , and where the line hits the vertical axis at $f = 0$ (green dashed) is the static floor $S = 1 mW$ — the power that would still flow even if the clock were fully stopped. This picture is the method: any $f$ -dependent power lives in the slope, any $f$ -independent power lives in the intercept.

Figure — Static vs dynamic power dissipation

Figure: total power versus clock frequency. Slope = switching (dynamic) coefficient; intercept at $f = 0$ = static (leakage) floor.

Answer: static floor $= 1 mW$ ; switching $= 4 mW$ per GHz of clock.

Level 4 — Synthesis

Combine multiple effects at once.

L4.1

A processor at $V_{D D} = 1.0 V$ has $P_{switching} = 3 W$ and $P_{static} = 1 W$ . Engineering lowers $V_{D D}$ to $0.7 V$ . Assume:

switching power $\propto V_{D D}^{2}$ ,
leakage current is roughly proportional to $V_{D D}$ (a simple linear model), so $P_{static} = I_{leak} V_{D D} \propto V_{D D}^{2}$ as well here.

Find the new $P_{switching}$ , new $P_{static}$ , and new total.

Recall Solution

The scaling ratio is $r = (0.7/1.0)^{2} = 0.49$ . $P_{switching,new} = 3 \times 0.49 = 1.47 W$ Under the stated linear-leakage model, $I_{leak} \propto V_{D D}$ and $P_{static} = I_{leak} V_{D D} \propto V_{D D}^{2}$ : $P_{static,new} = 1 \times 0.49 = 0.49 W$ $P_{total,new} = 1.47 + 0.49 = 1.96 W$ Answer: $1.47 W$ switching, $0.49 W$ static, $1.96 W$ total (down from $4 W$ ).

L4.2

Contrast with reality: leakage is not friendly. To keep the chip fast at $0.7 V$ , designers lower the threshold voltage $V_{T}$ , and subthreshold leakage grows exponentially (parent §4). Suppose lowering $V_{T}$ multiplies $I_{leak}$ by $10 \times$ on top of the linear- $V_{D D}$ drop from L4.1. What is the new static power now, and what fraction of the new total does it represent?

Recall Solution

From L4.1 the "linear-only" static was $0.49 W$ . Multiply by the $10 \times$ exponential blow-up: $P_{static,new} = 0.49 \times 10 = 4.9 W$ New total $= P_{switching} + P_{static} = 1.47 + 4.9 = 6.37 W$ . Static fraction: $\frac{4.9}{6.37} \approx 0.769 = 76.9%$ Answer: static jumps to $4.9 W$ , now $\approx 76.9%$ of the total — the chip actually got worse. This is the "leakage monster" of deep-nanometer nodes: naive voltage scaling that drags $V_{T}$ down can be swamped by exponential subthreshold current. See Threshold voltage and subthreshold conduction.

Level 5 — Mastery

Defend a full design decision with numbers.

L5.1 — Power gating decision

A block draws $P_{static} = 0.5 W$ whenever it is powered. It is only active $20%$ of the time. A power-gating sleep switch can fully cut its leakage during the idle $80%$ , but each wake-up costs a fixed energy overhead $E_{wake} = 5 mJ$ , and the block wakes up $50$ times per second.

(a) Without gating, what is the average leakage power wasted during idle time (i.e. leakage energy per second averaged over one second)? (b) With gating, what is the average wake-overhead power (wake energy per second)? (c) Is gating worth it?

Recall Solution

We compare two average powers (watts). "Average power" = energy spent over one second ÷ one second, so joules-per-second reads directly as watts.

(a) Idle fraction $= 0.80$ , so in each second the block is idle for $0.80 s$ , leaking at $0.5 W$ . Leakage energy per second $= 0.5 W \times 0.80 s = 0.4 J$ , spread over $1 s$ : $P_{idle,no gate} = \frac{0.5 W \times 0.80 s}{1 s} = 0.4 W$

(b) During sleep, leakage is cut to zero. But you pay wake overhead $50$ times per second. Wake energy per second $= 50 \times 5 \times 1 0^{- 3} J = 0.25 J$ , spread over $1 s$ : $P_{wake} = \frac{50 \times 5 \times 1 0 ^{- 3} J}{1 s} = 0.25 W$

(c) Compare the two average powers: $0.25 W < 0.4 W$ . Gating saves $0.4 - 0.25 = 0.15 W$ . Worth it here.

Answer: (a) $0.4 W$ , (b) $0.25 W$ , (c) yes — saves $0.15 W$ .

L5.2 — The break-even wake rate

Using the same block, at what wake-up rate $N$ (times per second) does power gating stop being worth it?

Recall Solution

WHY: gating wins while the average wake-overhead power is below the average leakage power saved. Break-even is where those two average powers are equal: $N \times E_{wake} = P_{static} \times (idle fraction)$ $N \times 5 \times 1 0^{- 3} = 0.5 \times 0.80 = 0.4$ $N = \frac{0.4}{5 \times 1 0 ^{- 3}} = 80 wake-ups per second$ Below $80$ wakes/s gating saves power; above $80$ the wake overhead dominates and gating costs you. Answer: break-even at $N = 80$ wake-ups per second.