Dennard scaling and its breakdown

WHAT is Dennard Scaling?

The idea: shrink everything consistently (called constant-field scaling) so the electric field inside the transistor stays the same. Same field → device physics behaves the same, just smaller and faster.

HOW: Deriving the scaling rules from first principles

We scale each geometric dimension by $1/k$ :

Channel length $L \to L/k$
Channel width $W \to W/k$
Oxide thickness $t_{ox} \to t_{ox}/k$
Supply voltage $V \to V/k$ (this keeps the field constant — the key trick)

Why scale voltage too? Electric field $\approx V/L$ . If we shrink $L$ by $k$ but keep $V$ fixed, the field jumps by $k$ → the tiny transistor gets fried. Scaling $V$ by $k$ too keeps $E = V/L$ constant. That's the "constant field" heart of it.

Step 1 — Capacitance

Gate capacitance is a parallel plate: $C_{ox} = \frac{\varepsilon_{ox}\,W L}{t_{ox}}$ Why this step? It's the physical capacitor formed by gate/oxide/channel.

Scale: $W\to W/k$ , $L\to L/k$ , $t_{ox}\to t_{ox}/k$ : $C' = \frac{\varepsilon_{ox}\,(W/k)(L/k)}{t_{ox}/k} = \frac{1}{k}C_{ox}$ So capacitance scales by $1/k$ . Why? Two length shrinks ( $1/k^2$ ) but thinner oxide raises $C$ by $k$ → net $1/k$ .

Step 2 — Current

Drive current (saturation, simplified): $I \approx \mu C_{ox}'' \frac{W}{L}(V-V_{th})^2, \quad C_{ox}''=\frac{\varepsilon_{ox}}{t_{ox}}$ Why this step? This is the square-law MOSFET current — the amount of charge moved per second.

Scale each factor: $C_{ox}''\to k\,C_{ox}''$ (thinner oxide), $W/L$ unchanged, $(V-V_{th})^2 \to (1/k)^2$ : $I' = k \cdot 1 \cdot \frac{1}{k^2} I = \frac{1}{k} I$ So current scales by $1/k$ .

Step 3 — Delay (speed)

Gate delay $\propto$ time to charge the capacitance: $\tau = \frac{C\,V}{I}$ Why this step? Delay = (charge to move)/(current) = $CV/I$ .

Scale: $C\to C/k$ , $V\to V/k$ , $I\to I/k$ : $\tau' = \frac{(C/k)(V/k)}{I/k} = \frac{1}{k}\,\tau$ So delay scales by $1/k$ → frequency $f\to k f$ . The chip gets $k\times$ faster. Free.

Step 4 — Power per device

Dynamic power $P = \tfrac{1}{2} C V^2 f$ . But for a clean "per device" number use $P = I V$ : $P' = I'V' = \frac{I}{k}\cdot\frac{V}{k} = \frac{1}{k^2} P$ So power per transistor scales by $1/k^2$ .

Step 5 — Power density (the punchline)

Area per device $A = WL \to (W/k)(L/k) = A/k^2$ . Power density: $\frac{P'}{A'} = \frac{P/k^2}{A/k^2} = \frac{P}{A} = \text{CONSTANT}$

That last box is the miracle: twice the transistors, twice the speed, same heat per $\text{mm}^2$ .

Figure — Dennard scaling and its breakdown

WHY it broke (~2005)

The derivation assumed $V$ could shrink freely and that transistors turn fully off. Both fail at small sizes.

Consequence: power density stopped being constant and started rising. Chips hit the power wall (~100–150 W/cm², near a hot plate). You physically cannot cool more.

Worked Examples

Common Mistakes (Steel-manned)

#flashcards/hardware

What does Dennard scaling keep constant as transistors shrink?

Power density (power per unit area),

P/A

What is "constant-field" scaling?

Scaling voltage

V

by the same factor

k

as dimensions so electric field

E=V/L

stays constant.

By what factor does gate delay scale under ideal Dennard scaling of factor

k

1/k

(chip is

k\times

faster), from

\tau = CV/I

By what factor does power per device scale under ideal Dennard?

1/k^2

, since

P=IV

and both

I,V

scale by

1/k

Why does capacitance scale by

1/k

not

1/k^2

C=\varepsilon WL/t_{ox}

; area gives

1/k^2

but thinner oxide gives

\times k

→ net

1/k

What physical limit stopped

V_{th}

from scaling?

Thermal voltage

kT/q\approx26

mV and exponential subthreshold leakage

I_{leak}\propto e^{-V_{th}/(nkT/q)}

Why did

V

freeze once

V_{th}

froze?

Need

V-V_{th}

headroom for drive current/speed, so

V

can't drop below a floor above

V_{th}

What is the "power wall"?

The ~100–150 W/cm² cooling limit that chips hit once power density stopped being constant.

What was the industry's response to Dennard breakdown?

Multicore CPUs (more cores at moderate clock) instead of ever-higher frequency; also 'dark silicon'.

Difference between Moore's Law and Dennard scaling?

Moore = transistor count doubles; Dennard = power density constant during shrink. Dennard died ~2005 first.

V

is frozen, how does power density scale with shrink

k

Roughly

k^3\times

(current up

\sim k

, voltage constant, area down

k^2

) — it rises, causing the power wall.

Recall Feynman: explain to a 12-year-old

Think of transistors as tiny water taps. Long ago, every time engineers made the taps smaller, they also turned down the water pressure by the same amount. Result: you could fit way more taps in the sink, they switched on/off faster, and the sink didn't get any hotter. Free upgrade! But there's a rule: a tap must fully turn off, or water leaks and wastes power. To turn off, it needs a minimum pressure — you can't go lower than that. So the pressure got stuck. Once you can't lower the pressure but keep cramming in more taps, the sink starts overheating. That's when they stopped making one super-fast tap and instead put in several medium taps (cores).

Connections

Moore's Law — count scaling; outlived Dennard scaling.
MOSFET Operation and Square-Law Current — source of $I\propto (V-V_{th})^2$ .
Subthreshold Leakage and Static Power — why $V_{th}$ can't drop.
Dynamic vs Static Power — $P_{dyn}=\tfrac12CV^2f$ used in Example 3.
Multicore and Dark Silicon — the industry's answer to breakdown.
Power Wall and Thermal Design Power (TDP) — the cooling ceiling.
Constant-Field vs Constant-Voltage Scaling — the two scaling philosophies.

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, Dennard scaling ka core idea simple hai: jab transistor ko chota karte ho factor $k$ se — length, width, oxide thickness sab $1/k$ — to voltage bhi $1/k$ karo. Isse andar ka electric field $E=V/L$ constant rehta hai, isliye ise "constant-field scaling" bolte hai. Iska magic result: delay $\tau=CV/I$ scale hota hai $1/k$ (chip $k\times$ fast), power per transistor girta hai $1/k^2$ , aur transistor count badhta hai $k^2$ . In dono ka product $=1$ , matlab power density (heat per mm²) same rehti hai. Isiliye 30 saal tak har naye node pe free mein faster + zyada transistors milte the, bina extra heat ke.

Ab breakdown kyun hua (~2005)? Problem $V_{th}$ (threshold voltage) ki thi. Transistor ko poora OFF karne ke liye $V_{th}$ ko thermal voltage $kT/q\approx26$ mV se kaafi upar rakhna padta hai, warna subthreshold leakage exponentially badh jaati hai ( $I_{leak}\propto e^{-V_{th}/(nkT/q)}$ ). Isliye $V_{th}$ neeche nahi gaya, aur jab $V_{th}$ ruk gaya to $V$ bhi ruk gaya (kyunki speed ke liye $V-V_{th}$ headroom chahiye). Voltage knob khatam!

Jab $V$ freeze ho gaya, to power density constant rehna band ho gaya — ab shrink karne pe heat badhne lagi (roughly $k^3\times$ ). Yahi "power wall" hai — around 100–150 W/cm², cooling practically impossible. Solution kya nikala? Ek super-fast core banane ki jagah multiple cores (multicore) moderate frequency pe. Yaad rakho: Moore's Law aur Dennard scaling alag cheezein hain — Moore count ke baare mein hai (abhi bhi chal raha), Dennard power density ke baare mein tha (2005 mein mar gaya). Isiliye aajkal GHz badhne ki jagah cores badhte hain.

Quantity	Scales by
Length, width, $t_{ox}$ , $V$	$1/k$
Capacitance $C$	$1/k$
Current $I$	$1/k$
Delay $\tau$ / speed	$1/k$ / $k\times$ faster
Power/device $P$	$1/k^2$
Device density	$k^2$
Power density $P/A$	$\boxed{1}$ (constant)

WHAT is Dennard Scaling?

HOW: Deriving the scaling rules from first principles

Step 1 — Capacitance

Step 2 — Current

Step 3 — Delay (speed)

Step 4 — Power per device

Step 5 — Power density (the punchline)

WHY it broke (~2005)

Worked Examples

Common Mistakes (Steel-manned)

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — VLSI Design

Connections