WHY it's not a physical law: Nothing in physics forces doubling. It is a self-fulfilling economic/industry roadmap — the semiconductor industry set targets and R&D budgets to keep the trend going. It holds because of engineering effort, not natural necessity.
WHAT quantity actually doubles: transistor count per chip — driven by shrinking the minimum feature size (the "node", e.g. 7 nm, 5 nm, 3 nm).
We want a formula for transistor count vs. time. Start from the rule: multiply by 2 every Td years (the doubling time).
Let N0 = transistors at year t0, and t = current year.
Number of doublings that have happened:
n=Tdt−t0
Each doubling multiplies by 2, so after n doublings:
N(t)=N0⋅2(t−t0)/Td
Why it looks linear on a log plot: Take log10:
log10N(t)=log10N0+Tdt−t0log102
This is a straight line in t with slope Tdlog102. That is why Moore's Law is always drawn on a semi-log graph — the exponential becomes a diagonal line.
Moore's Law says "more transistors." Dennard scaling (1974) explains why those smaller transistors were also faster and cooler. This is the physics engine behind the golden age of scaling.
Setup: Scale every dimension (length L, width W, oxide thickness tox) and the voltage V down by the same factor κ>1 (e.g. κ=1.4=2 per node — halves area each node).
Derive the consequences from device physics:
Quantity
Relation
Scales as
Area
A=L⋅W
1/κ2
Gate capacitance
C=εtoxWL
1/κ
Voltage
V
1/κ
Current
I∝LW(V)2-ish, →
1/κ
Gate delay
τ=ICV
1/κ (faster!)
Power/transistor
P=21CV2f,∝CV2
1/κ2
Power density
P/A=AP
1/κ21/κ2=1constant!
Derivation of gate delay (Why τ∝1/κ):
τ=ICV=(1/κ)(1/κ)(1/κ)=κ1
Delay shrinks → clock frequency rises. This is why CPU clocks screamed upward through the 1990s.
If V = constant while transistors keep doubling:
AP∝ACV2f↑(power density now RISES per node)
This is the Power Wall → chips would melt. Industry's response: stop raising clock frequency, go multi-core instead. (Same transistor budget spent on parallelism, not speed.)
Moore's Law (transistor count) continued via FinFETs, GAA, 3D stacking — but Dennard scaling died, which is why single-thread speed stalled.
Imagine LEGO bricks that get half as wide every couple of years. Suddenly you can fit twice as many bricks in the same box! That means you can build a much cooler LEGO castle every 2 years without a bigger box. For a long time the tiny bricks also snapped together faster and stayed cool. But eventually the bricks got SO tiny that they started leaking heat and couldn't be squeezed more without catching fire — so instead of making one super-fast castle, builders now make many castles side by side (that's "multi-core").
Transistor count on an economically optimal chip doubles ~every 2 years (empirical observation, not a physical law).
What is the transistor-growth formula?
N(t)=N02(t−t0)/Td with Td≈2 years.
Why is Moore's Law plotted on a semi-log axis?
Because logN is linear in time, so exponential growth appears as a straight line.
What does Dennard scaling describe (vs Moore's Law)?
How shrinking transistors makes them faster and lower-power, keeping power density constant — the physics behind why more transistors were also better.
How does gate delay scale under Dennard scaling?
τ=CV/I∝1/κ — smaller = faster.
How does power density scale under ideal Dennard scaling?
Constant (P/A stays ~fixed).
When and why did Dennard scaling end?
~2005; voltage couldn't scale below ~1 V without exploding leakage current, so power density began rising (power wall).
What was the industry response to the power wall?
Stop raising clock frequency; go multi-core (parallelism instead of speed).
What is "dark silicon"?
Portions of a chip that must stay powered off because you can't power all transistors simultaneously within the thermal budget.
Is "5 nm" a real physical feature size today?
No — it's a marketing/node label, not a literal measured length.
If a design shrinks by node factor κ=2, what happens to area?
Dekho, Moore's Law koi physics ka rule nahi hai — ye ek observation hai jo Gordon Moore ne 1965 me di. Baat simple hai: har lagbhag 2 saal me ek chip par transistors ki sankhya double ho jaati hai. Formula yaad rakho: N(t)=N02(t−t0)/2. Isko log-scale par plot karo to seedhi line ban jaati hai — kyunki exponential growth log lene par linear ho jaati hai. Yahi reason hai ki Moore's Law ka graph hamesha semi-log par dikhaya jaata hai.
Ab ek important cheez: Moore's Law sirf count ki baat karta hai, "zyada transistors". Lekin transistors chhote hone se tez aur thande kyun huye — wo Dennard scaling explain karta hai. Jab tum length, width aur voltage sabko factor κ se chhota karte ho, to delay τ=CV/I ghatta hai (chip tez), aur power density constant rehti hai. Matlab same area me double transistors, no extra heat — bilkul free lunch!
Par ye party ~2005 me khatam ho gayi. Voltage ko 1 V se neeche laane par leakage current exponentially badh jaati hai, isliye voltage scale hona ruk gaya. Constant voltage par jab transistors double karo, to power density badhne lagti hai — isko power wall kehte hain. Chip garmi se pighalne lagti. Isliye industry ne clock speed badhana chhod diya aur multi-core ki taraf move ho gayi — ek fast core ke bajaye kai cores.
Exam aur interview me ye distinction poochha jaata hai: Moore = MORE (count double), Dennard = FASTER + COOLER (physics). Moore's Law abhi bhi FinFET, 3D stacking se chal rahi hai (thodi slow), par Dennard scaling mar chuki hai — isiliye tumhare laptop ka clock speed pichle 15 saal se ~3-4 GHz par atka hua hai.
