Before you can read the parent note, you must be able to read every squiggle in it. Below is a strict, build-from-zero tour of each symbol and idea the parent uses. Nothing later depends on something not yet defined. If you know all of these, jump back to Moore's Law and scaling trends.
The picture: think of a water tap. The gate is the handle; turning it lets water (current) through or blocks it. That's all a transistor is at this level.
Why the topic needs it: Moore's Law counts these. Everything else — area, power, delay — is a property of one of these switches.
Figure 1 — A transistor drawn as a switch: source and drain (mint) joined by a channel (butter), with the gate (lavender) on top acting like a tap handle that opens or blocks the current flow (coral arrows).
The picture: look at the transistor as a little rectangle on the chip. L and W are its two side lengths; multiply them and you get the floor space A it eats up.
Why we need it: "make transistors smaller" literally means shrink L, W, tox. If area A halves, twice as many fit in the same silicon — that is the mechanical reason Moore's Law can happen.
Figure 2 — Left: top view of the transistor rectangle showing length L (coral) and width W (lavender), with area A=L×W. Right: side view showing the thin oxide thickness tox between the gate (lavender) and the silicon channel (mint).
The picture: a tree that splits in two at every step. After 1 split there are 2 branches, after 2 splits 4, after 5 splits 32. The exponent is "how many split-levels down you are".
Why this tool and not plain multiplication? Because the growth is repeated multiplication, not repeated addition. If you only added a fixed number of transistors each year you'd get a straight line. Real chips multiply, so you must use an exponent to capture it. That is why the topic is "exponential", not "linear".
The picture: a stopwatch that started at year t0. Every time Td years tick by, the transistor count doubles. N0 is the reading at the start; N(t) is the reading now.
Building the formula from §3: in §3 we saw "n doublings" gives a multiplier 2n. Here the number of doublings is just "years passed divided by doubling time", n=(t−t0)/Td. Multiply the starting count N0 by that 2n and you get exactly N(t)=N02(t−t0)/Td.
Why the subscript "0"? The little 0 just means "the reference value we start from". It is not a special zero — it labels the anchor point of the stopwatch.
To solve for an unknown exponent. In Example 2 the parent must solve 222/Td=103. The unknown Td is stuck up in the exponent. Taking log10 of both sides drops it down where algebra can reach it:
Td22log102=3.
To make the graph a straight line. Taking log10 of the growth formula gives
log10N(t)=log10N0+Tdt−t0log102,
which has the shape "constant + (slope)×t" — a straight line. That is why Moore's Law is drawn on a semi-log graph: the exponential curve becomes a diagonal you can read with a ruler.
Figure 3 — The same growth curve twice. Left (coral, linear axis): the exponential shoots up and is hard to read. Right (lavender, semi-log axis): the very same data becomes a straight line whose slope is (log102)/Td.
The picture: a photocopy set to "shrink to 1/κ". Every length on the transistor comes out κ times smaller.
Why ∝ and not =? Take capacitance, which the parent writes as C=εtoxWL. Here ε (epsilon) is just a fixed material constant — a property of the oxide that never changes as we shrink. Because ε is the same before and after, it cancels when we compare "after / before". We don't care about its exact value — only about whether shrinking makes C bigger or smaller and by how much. ∝ strips away that constant clutter so the trend is visible.
Each of these is a property of a switching transistor. Define them once, then the whole Dennard table reads easily.
Why "power density" P/A? A big cool chip and a tiny hot chip can burn the same total watts but the tiny one melts because the heat is squeezed into less area. So the quantity that decides "does it melt?" is P/A — power per unit area — which is why the parent tracks it, not P alone.
Figure 4 — The bucket analogy: capacitance C is the bucket size, current I is the fill-flow (coral), voltage V is the pressure it fills to (lavender). Delay τ=CV/I is the time to fill; power P∝CV2f is filling and emptying f times a second.
Why this ends the free lunch: To keep the "cool" benefit, voltage V had to keep shrinking. But V can't drop below what Vth allows without leakage exploding — so V froze around 2005, and the constant-power-density magic stopped. That is the power wall that pushed everyone toward Multi-core Architecture.
The map below shows the build order: each box is one section above, and an arrow means "you need this before that". The two spines — the exponential/log spine and the physical-quantity spine — meet at the power wall.