Moore's Law and scaling trends: Worked examples — Hardware deep dive

Every symbol used here was defined in the parent; we re-anchor each one the moment it appears.

The scenario matrix

Here is the full space of questions this topic throws. Each row is a case class; the last column names the worked example that covers it.

#	Case class	What makes it distinct	Covered by
A	Forward count — given start + time, find $N$	plug into $N_{0} 2^{(t - t_{0}) / T_{d}}$ directly	Example 1
B	Backward time — given growth ratio, find elapsed years	invert the exponent with a log	Example 2
C	Backward doubling time — given two data points, find $T_{d}$	solve for the parameter, not the output	Example 3
D	Non-integer / fractional doublings — time not a whole multiple of $T_{d}$	exponent is a fraction; result is not a round ×2	Example 4
E	Degenerate input — $t = t_{0}$ , or $T_{d} \to \infty$ (stagnation)	exponent = 0 or → 0; growth stops	Example 5
F	Log-plot / slope — read Moore's line off a semi-log graph	slope $= \frac{l o g _{10} 2}{T _{d}}$ , a geometry question	Example 6 (figure)
G	Dennard forward — one node, find speed & area change	scale by $κ$ across the physics table	Example 7
H	Post-Dennard limiting case — $V$ frozen, power density behaviour	the "wall": ratio no longer cancels	Example 8
I	Real-world word problem — cores vs clock trade-off	translate English → which engine applies	Example 9
J	Exam twist — mixes a false premise (node name, "faster")	spot the trap before computing	Example 10

We now clear the whole matrix, one example per row.

Case A — forward count

Worked example Example 1 (Cell A) — Transistors 12 years out

A chip has $N_{0} = 5 \times 1 0^{8}$ transistors in 2018. With doubling time $T_{d} = 2$ years, predict the count in 2030.

Forecast: guess first — is it closer to $10 \times$ , $30 \times$ , or $60 \times$ the start?

Count the doublings. Elapsed time $t - t_{0} = 2030 - 2018 = 12$ years. Number of doublings $n = \frac{12}{2} = 6$ . Why this step? The exponent in $N_{0} 2^{(t - t_{0}) / T_{d}}$ is literally "how many doubling periods fit in the elapsed time." $12/2 = 6$ periods.
Apply the multiplier. Each doubling is $\times 2$ , so total factor $= 2^{6} = 64$ . Why this step? Repeated multiplication by 2, six times, is $2^{6}$ — that is what the exponential encodes.
Multiply. $N = 5 \times 1 0^{8} \times 64 = 3.2 \times 1 0^{10}$ .

Verify: $3.2 \times 1 0^{10} /5 \times 1 0^{8} = 64 = 2^{6}$ ✓, and 6 doublings over 12 years is exactly $T_{d} = 2$ ✓. (Answer beats the $30 \times$ guess — exponentials feel bigger than intuition.)

Case B — backward for time

Worked example Example 2 (Cell B) — How long to grow 1000×?

Transistor count grows from $2 \times 1 0^{6}$ to $2 \times 1 0^{9}$ . With $T_{d} = 2$ yr, how many years passed?

Forecast: $1000 \times$ — more or fewer than 20 years?

Form the ratio. $\frac{N}{N _{0}} = \frac{2 \times 1 0 ^{9}}{2 \times 1 0 ^{6}} = 1 0^{3}$ . Why this step? $N_{0}$ cancels, leaving pure growth — the ratio is all that matters for elapsed time.
Set up the equation. $2^{(t - t_{0}) / T_{d}} = 1 0^{3}$ . Why this step? $N / N_{0} = 2^{(t - t_{0}) / T_{d}}$ from the growth law; substitute the ratio.
Take $lo g_{10}$ to free the exponent. $\frac{t - t _{0}}{T _{d}} lo g_{10} 2 = 3$ . Why a log, and why base 10? The unknown $t - t_{0}$ is trapped in an exponent. A logarithm is the exact tool that "brings an exponent down" ( $lo g a^{b} = b lo g a$ ). Base 10 because $lo g_{10} 1 0^{3} = 3$ is clean.
Solve. $t - t_{0} = \frac{3 T _{d}}{lo g _{10} 2} = \frac{3 \times 2}{0.30103} \approx 19.9$ years.

Verify: $19.9/2 \approx 9.97$ doublings, $2^{9.97} \approx 1000$ ✓. Roughly "1000× ≈ 10 doublings ≈ 20 years" — a useful mental shortcut.

Case C — backward for the doubling time

Case D — fractional doublings

Case E — degenerate / stagnation limits

Worked example Example 5 (Cell E) — Zero time and infinite doubling time

Two edge cases. (a) Predict $N$ at the same year, $t = t_{0}$ . (b) What happens as scaling stalls, i.e. $T_{d} \to \infty$ ?

Forecast: should either case ever change $N$ ?

Case (a): $t = t_{0}$ . Exponent $= \frac{t - t _{0}}{T _{d}} = \frac{0}{2} = 0$ , and $2^{0} = 1$ , so $N = N_{0} \cdot 1 = N_{0}$ . Why this step? No time has passed, so no doublings occurred. Any nonzero base to the 0 power is 1 — the maths agrees that nothing changes.
Case (b): $T_{d} \to \infty$ . Exponent $\frac{t - t _{0}}{T _{d}} \to 0$ for any finite elapsed time, so $2^{\to 0} \to 1$ , giving $N \to N_{0}$ . Why this step? An infinite doubling time means "it never doubles" — the curve flattens into a horizontal line. This is precisely the stagnation / end-of-scaling scenario: growth freezes.

Verify: both degenerate inputs return $N_{0}$ , matching physical sense (no elapsed doublings ⇒ no change). The limit $T_{d} \to \infty \Rightarrow$ flat line is exactly what a slowing Moore's Law looks like on the graph. ✓

Case F — reading the semi-log line

The parent said Moore's Law is drawn on a semi-log graph. A semi-log plot puts $lo g_{10} N$ on the vertical axis but ordinary years on the horizontal — so the exponential $N (t) = N_{0} 2^{(t - t_{0}) / T_{d}}$ becomes the straight line

$lo g_{10} N (t) = lo g_{10} N_{0} + slope \frac{lo g _{10} 2}{T _{d}} (t - t_{0}) .$

The slope is a pure geometry fact you can read off the graph. Look at the figure below.

Worked example Example 6 (Cell F) — Recover

$T_{d}$ from a line's slope On a semi-log transistor plot, the line rises by 1 decade ( $lo g_{10} N$ increases by 1, i.e. $N \times 10$ ) every 6.64 years. Find $T_{d}$ .

Forecast: slope is fixed by $T_{d}$ alone — will it come out near 2 years?

Slope from the graph. slope $= \frac{Δ ( lo g _{10} N )}{Δ t} = \frac{1}{6.64} decades/yr$ . Why this step? "Rise over run" on the semi-log axes is the slope; here rise is measured in decades of $N$ .
Match to the formula. slope $= \frac{lo g _{10} 2}{T _{d}}$ , so $\frac{lo g _{10} 2}{T _{d}} = \frac{1}{6.64}$ . Why this step? The algebraic slope of the line equals the graphical slope — equate them to solve for $T_{d}$ .
Solve. $T_{d} = 6.64 \times lo g_{10} 2 = 6.64 \times 0.30103 \approx 2.0$ years.

Verify: one decade ( $\times 10$ ) needs $lo g_{2} 10 \approx 3.32$ doublings; $3.32 \times 2 = 6.64$ yr ✓. The slope-to- $T_{d}$ conversion is self-consistent.

Case G — Dennard scaling forward

Worked example Example 7 (Cell G) — One node: speed and area

Take one process node with scaling factor $κ = 2$ . Using Dennard Scaling, find how area, gate delay, and per-transistor power change. (Recall from the parent: area $\propto 1/ κ^{2}$ , delay $τ = C V / I \propto 1/ κ$ , power $\propto C V^{2} \propto 1/ κ^{3}$ … with $f$ as the switch rate in Dynamic Power CV2f.)

Forecast: does density double and speed rise together?

Area. $A \propto 1/ κ^{2} = 1/ (2)^{2} = 1/2$ . Why this step? Both length $L$ and width $W$ shrink by $κ$ , and area is $L \cdot W$ , so it shrinks by $κ^{2}$ . Half the area = double the density — one Moore doubling per node.
Gate delay. $τ \propto 1/ κ = 1/ 2 \approx 0.707$ . Why this step? $τ = C V / I$ with $C \propto 1/ κ$ , $V \propto 1/ κ$ , $I \propto 1/ κ$ gives $τ \propto \frac{( 1/ κ ) ( 1/ κ )}{1/ κ} = 1/ κ$ . Delay dropping means clock can rise by $1/0.707 \approx 1.414 \times$ — ~1.4× faster.
Power density. $\frac{P}{A} \propto \frac{C V ^{2}}{A} = \frac{( 1/ κ ) ( 1/ κ ) ^{2}}{1/ κ ^{2}} = \frac{1/ κ ^{3}}{1/ κ ^{2}} = \frac{1}{κ}$ … but $f$ also rises by $κ$ , restoring $P / A \approx$ constant. Why this step? The famous Dennard cancellation: more, faster, hotter-per-switch transistors, yet the heat per unit area stays flat.

Verify: area $1/2$ ✓ (matches "double density"), delay $0.707$ ✓ (⇒ $1.41 \times$ speed), power density ratio $\to 1$ ✓. This is the "free lunch" node.

Case H — the post-Dennard limiting case

Worked example Example 8 (Cell H) — Voltage frozen: what breaks?

After ~2005, $V$ can no longer shrink (or leakage explodes). Keep $κ = 2$ shrinking of dimensions but hold $V$ constant. Find the new power-density trend across a node.

Forecast: does power density stay flat, or start climbing?

Which factors still scale? Capacitance $C \propto 1/ κ$ (geometry still shrinks), but $V =$ const now. Why this step? Dennard's cancellation relied on $V \propto 1/ κ$ . Freeze $V$ and one factor drops out of the chain.
Per-transistor dynamic power. $P \propto C V^{2} f \propto (1/ κ) (1) (κ) = 1$ → per transistor power roughly constant, not falling. Why this step? With $V$ fixed and $f$ up by $κ$ , the $1/ κ$ from $C$ just cancels $f$ — no more per-device reduction.
Power density. Transistor count per area doubles ( $\times κ^{2}$ ) while each burns the same power, so $P / A \propto κ^{2} /1 = κ^{2} = 2$ per node — doubles. Why this step? No voltage relief means twice the transistors in the same area = twice the heat. That is the Power Wall.

Verify: $P / A$ ratio $= (2)^{2} = 2 > 1$ ✓ — density rises, forcing the switch to Multi-core Architecture instead of higher clocks. Contrast Example 7 where the ratio was 1.

Case I — real-world word problem

Worked example Example 9 (Cell I) — Cores instead of clock

A 2005 design has a transistor budget that just doubled (one Moore node). Dennard is dead, so you cannot raise the clock. If you spend the extra transistors on duplicate cores, how does ideal throughput change vs. the alternative of one bigger core?

Forecast: which uses the doubled budget better under a fixed power ceiling?

Translate to which engine. "Transistor count doubled" = Moore applies. "Can't raise clock" = Dennard dead, CMOS $V$ frozen. Why this step? The parent's core distinction: Moore gives more, Dennard gave faster. Only Moore is still alive here.
Two-core throughput. Two identical cores at the same clock ⇒ ideal parallel throughput $\times 2$ (embarrassingly parallel work). Why this step? Doubling identical units doubles work done per second if the workload parallelises — no clock increase needed.
One-bigger-core alternative. A single core with $2 \times$ transistors does not give $2 \times$ single-thread speed — diminishing returns, and clock is capped by the power wall. Why this step? Serial speed is limited by the frozen clock; extra transistors on one core buy far less than $2 \times$ .

Verify: two cores → up to $2.0 \times$ throughput on parallel work; one big core → well under $2 \times$ . This is exactly why 2005+ chips went multi-core. Units check: throughput ratio is dimensionless, $2 \times$ ✓.

Case J — the exam twist (spot the trap)

Worked example Example 10 (Cell J) — "A 3 nm chip's clock doubles every 2 years"

Exam claim: "By Moore's Law, a 3 nm chip's clock speed doubles every 2 years, and 3 nm means the gate is literally 3 nm long." Two traps. Compute what Moore's Law actually predicts for a $1 0^{10}$ -transistor chip over 4 years, and correct both false premises.

Forecast: how many of the two claims survive?

Trap 1 — "clock doubles." Moore's Law is about transistor count, not clock. Post-Dennard, clock is roughly flat (~3–4 GHz). Why this step? The parent's headline mistake: conflating Moore (count) with Dennard (speed). Clock doubling died with Dennard ~2005.
Correct computation — count only. Over 4 years, $n = 4/2 = 2$ doublings, factor $2^{2} = 4$ . $N = 1 0^{10} \times 4 = 4 \times 1 0^{10}$ . Why this step? Apply the valid part of the claim (count) with the standard law.
Trap 2 — "3 nm is a physical length." Modern node names are marketing labels; no single feature is literally 3 nm (see FinFET and Gate-All-Around for why geometry ≠ node name). Why this step? The parent explicitly warns node names are not real gate lengths.

Verify: correct count $= 4 \times 1 0^{10}$ ( $= 2^{2} \times 1 0^{10}$ ) ✓; both stated premises are false (clock ≠ doubling, node ≠ physical length). Only "count grows" survives.

Recall Which cell am I in?

Given start + time, find count ::: Cell A — forward, plug in. Given growth ratio, find years ::: Cell B — take a log. Given two data points, find $T_{d}$ ::: Cell C — solve for the parameter. Time not a whole multiple of $T_{d}$ ::: Cell D — fractional exponent, use $2^{1.5} = 22$ . $t = t_{0}$ or $T_{d} \to \infty$ ::: Cell E — exponent → 0, $N \to N_{0}$ (stagnation). Reading a semi-log slope ::: Cell F — slope $= lo g_{10} 2/ T_{d}$ . One node speed/area ::: Cell G — Dennard, scale by $κ$ . $V$ frozen, power density ::: Cell H — cancellation breaks, $P / A$ rises. Cores vs clock ::: Cell I — Moore alive, Dennard dead. "Clock doubles / 3 nm is real" ::: Cell J — both false premises.

Active Recall

What is the transistor multiplier after

n

whole doublings?

2^{n}

Over 4 years with

T_{d} = 2

, by what factor does count grow?

2^{4/2} = 2^{2} = 4 \times

How do you free the unknown from an exponent?

Take a logarithm —

lo g a^{b} = b lo g a

What does a half-doubling (

2^{0.5}

) multiply by?

2 \approx 1.414

On a semi-log Moore plot, what does the slope equal?

lo g_{10} 2/ T_{d}

Under ideal Dennard scaling with

κ = 2

, what is the delay factor?

1/ 2 \approx 0.707

(⇒ ~1.4× faster).

With

V

frozen, how does power density scale per node (

κ = 2

It doubles (

κ^{2} = 2

) — the power wall.