Moore's Law and scaling trends: Question bank — Hardware deep dive

Before you start, make sure the vocabulary is grounded. If any of these words feel fuzzy, the trap will catch you:

Transistor count — how many switches are etched on one chip.
Node (e.g. "5 nm") — the marketing name of a manufacturing generation.
Doubling time $T_{d}$ — years between successive $\times 2$ of transistor count.
$κ$ (kappa) — the scaling factor ( $> 1$ ) by which every dimension and the voltage shrink each node.
Power density $P / A$ — power (watts) divided by chip area; how hot each square millimetre runs.
Threshold voltage $V_{t h}$ — the gate voltage at which a CMOS Transistor flips from "off" to "on".

True or false — justify

Moore's Law is a fundamental law of physics.

False. It is an empirical economic/industry observation; nothing in physics forces doubling — it held because companies budgeted R&D to make it hold.

Moore's Law by itself guarantees that chips get faster every 2 years.

False. Moore's Law is strictly about transistor count; the historical speed gains came from Dennard Scaling, a separate mechanism that ended ~2005.

Under ideal Dennard scaling, power density stays roughly constant across nodes.

True. Power per transistor falls as

1/ κ^{2}

and area also falls as

1/ κ^{2}

, so their ratio

P / A

stays ~fixed — that constancy was the "free lunch".

After Dennard scaling ended, Moore's Law also immediately stopped.

False. Transistor count kept doubling via FinFETs and GAA and 3D stacking; only the speed/power benefit (Dennard) died.

A "5 nm" node means the transistor's gate is physically 5 nm long.

False. Modern node names are marketing labels; no single feature literally measures 5 nm — the name is a generation tag, not a length.

On a semi-log plot, Moore's Law appears as a straight line.

True. Taking

lo g_{10}

N = N_{0} 2^{(t - t_{0}) / T_{d}}

gives

lo g N

linear in

t

, so the exponential straightens into a diagonal.

Threshold voltage

V_{t h}

could keep shrinking as fast as the other dimensions.

False. Drop

V_{t h}

too far and subthreshold leakage explodes exponentially (Leakage Current and Subthreshold Conduction), so voltage scaling stalled — this is what broke Dennard scaling.

Going multi-core was a choice to increase single-thread speed.

False. Multi-core Architecture was the response to the power wall: the same transistor budget was spent on parallel cores because clocks could no longer safely climb.

Halving the voltage under Dennard scaling roughly quarters the dynamic power per transistor.

True. Dynamic power (Dynamic Power CV2f)

\propto C V^{2}

; if

V \to V / κ

and

C \to C / κ

, power scales as

1/ κ^{3}

per switch, and with

f

rising it lands at

1/ κ^{2}

— a strong drop.

Dark silicon means the chip has manufacturing defects.

False. Dark silicon means you cannot power all transistors at once within the thermal budget, so parts stay switched off ("dark") — a power limit, not a defect.

Spot the error

"Because transistors doubled, clock speed doubled too — that's Moore's Law."

The error conflates count with speed. Doubling count is Moore's Law; the speed gain was Dennard Scaling (delay

τ \propto 1/ κ

), which is a distinct, now-dead mechanism.

"Power density stays constant no matter what, because it always did in the 1990s."

Constant

P / A

required voltage to scale down with size. Once

V

froze near ~1 V,

P / A

started rising per node — the power wall.

"Since the node shrank from 7 nm to 5 nm, the actual gate got 2 nm shorter."

Node names are not physical lengths; you cannot subtract them to get a real dimension. The label tracks a generation, not a measured feature.

"Delay scales as

τ = C V / I

, and since everything shrinks, delay is unchanged."

Wrong cancellation.

C \to 1/ κ

V \to 1/ κ

I \to 1/ κ

, so

τ = \frac{( 1/ κ ) ( 1/ κ )}{1/ κ} = 1/ κ

— delay shrinks, transistors get faster.

"We can keep raising clock frequency forever by adding more transistors."

More transistors at constant voltage raises power density until the chip can't dissipate the heat. That thermal ceiling (power wall) is exactly why frequency plateaued at ~3–4 GHz.

"Moore's Law predicts

N_{0} \cdot 2^{t / T_{d}}

, so at

t = 0

we already have

2

transistors."

The exponent must be measured from a reference year

t_{0}

N = N_{0} 2^{(t - t_{0}) / T_{d}}

. At

t = t_{0}

the exponent is

0

and

N = N_{0}

, not

2

Why questions

Why is Moore's Law drawn on a semi-log axis instead of a linear one?

Because

lo g N

is linear in time, a straight line is easy to read, extrapolate, and fit; on a linear axis the early decades would be crushed flat against the bottom.

Why did smaller transistors used to be better and not merely more numerous?

Dennard Scaling: shrinking dimensions and voltage together cut gate delay (

\propto 1/ κ

) and power per device (

\propto 1/ κ^{2}

), so each new node was faster and cooler, not just denser.

Why did voltage scaling stop, killing the free lunch?

Lowering supply voltage forces

V_{t h}

down too, but below ~1 V that unleashes exponential subthreshold leakage, so voltage froze and constant power density became impossible.

Why does the base of the exponential equal exactly 2?

Because "doubles every

T_{d}

" means multiply by 2 each interval; the base literally encodes the doubling rule, while the exponent

(t - t_{0}) / T_{d}

counts how many doublings have occurred.

Why did the industry go multi-core rather than keep pushing GHz?

Once the power wall capped frequency, the doubling transistor budget was better spent on parallel cores — total throughput could still rise even though single-thread clock could not.

Why is Moore's Law called "self-fulfilling"?

Companies set roadmaps and R&D targets to the trend, so the observation shaped investment which in turn kept the observation true — cause and effect loop, not natural inevitability.

The formula diverges to infinity, but atoms have finite size and heat has finite limits, so unbounded exponential growth must eventually saturate — the model is a local approximation, not an eternal law.

κ < 1

were plugged in (transistors grew instead of shrank), what would delay do?

Delay

\propto 1/ κ

would increase, meaning slower transistors — correctly capturing that bigger devices switch more sluggishly.

Recall One-line self-test

Cover every answer above and re-derive the reason, not the verdict. If you can only recall "true/false" without the mechanism, that trap will still catch you on an exam.

Question bank — Moore's Law and scaling trends

True or false — justify

Spot the error

Why questions

Edge cases