Subthreshold leakage current

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WHAT is it?

WHY does any current flow below threshold? The threshold voltage $V_{th}$ is a convention, not a physical cliff. Below it the surface potential is still bending the bands; a Boltzmann-small fraction of electrons has enough thermal energy to populate the surface. Since that fraction $\propto e^{\,q\psi_s/kT}$, and $\psi_s$ moves with $V_{GS}$, the current is exponential in $V_{GS}$.

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HOW to derive it from scratch

The channel below threshold behaves like the base of a BJT: carriers diffuse across from source to drain. Start from the diffusion current of electrons:

$I_{sub} = q\,A\,D_n\,\frac{dn}{dx} \approx q\,A\,D_n\,\frac{n(0)-n(L)}{L}$

Why this step? Weak inversion → negligible drift field along the channel → transport is diffusion, exactly like minority carriers in a BJT base.

The carrier concentration at the source end of the surface is set by the surface potential $\psi_s$ via Boltzmann statistics:

$n(0) \propto e^{\,q\psi_s / kT}$

Why this step? In thermal equilibrium the band bending $\psi_s$ raises the electron population by a Boltzmann factor — this is the source of the exponential.

Now, how does $\psi_s$ depend on the gate? The gate voltage divides between the oxide capacitance $C_{ox}$ and the depletion capacitance $C_{dep}$ (a capacitive divider):

$\frac{d\psi_s}{dV_{GS}} = \frac{C_{ox}}{C_{ox}+C_{dep}} = \frac{1}{n}, \qquad n \equiv 1 + \frac{C_{dep}}{C_{ox}}$

Why this step? Not all of $V_{GS}$ reaches the surface — some is dropped across the depletion layer. $n$ is the body-effect / subthreshold slope factor, typically $1.1$–$1.5$.

Combine: $n(0) \propto e^{\,q V_{GS}/(nkT)}$. Putting it together and adding the drain-voltage dependence (the drain end depletes carriers, $n(L)\propto e^{-qV_{DS}/kT}$):

The subthreshold swing $S$

WHAT: how many millivolts of $V_{GS}$ you must remove to cut $I_{sub}$ by a factor of 10.

Take $\log_{10}$ of $I_{sub}$ and invert the slope:

\;\Rightarrow\; S = \frac{dV_{GS}}{d(\log_{10}I_{sub})}$$ > [!formula] Subthreshold swing > $$\boxed{\,S = n\,V_T\ln 10 = \left(1+\frac{C_{dep}}{C_{ox}}\right)\frac{kT}{q}\ln 10\,}$$ > At 300 K, the **ideal** ($n=1$) limit is $S_{min}= V_T\ln 10 \approx 60\ \text{mV/decade}$. > [!intuition] Why 60 mV/dec is a wall > $\ln 10$ and $kT/q$ are fixed by physics. You *cannot* beat 60 mV/dec with an ordinary MOSFET at room temperature — this is the "Boltzmann tyranny" that limits how low $V_{DD}$ can go. (Exotic devices like tunnel-FETs try to break it.) ![[2.4.17-Subthreshold-leakage-current.png]] --- ## Worked examples > [!example] 1 — Compute the swing > A transistor has $C_{ox}=2C_{dep}$, i.e. $C_{dep}/C_{ox}=0.5$, at 300 K. > - $n = 1 + 0.5 = 1.5$. *Why?* Definition of slope factor. > - $V_T = 25.9$ mV. *Why?* $kT/q$ at 300 K. > - $S = 1.5 \times 25.9 \times 2.303 \approx 89.5$ mV/decade. > **Interpretation:** dropping $V_{GS}$ by ~90 mV cuts leakage 10×. > [!example] 2 — Leakage ratio between two bias points > Same device, $n=1.5$, $V_T=25.9$ mV. How much bigger is leakage when the gate sits 120 mV *below* $V_{th}$ vs 300 mV below? > $$\frac{I(-120)}{I(-300)} = \exp\!\left(\frac{-0.120-(-0.300)}{1.5\times0.0259}\right)=\exp\!\left(\frac{0.180}{0.0389}\right)=e^{4.63}\approx 102.$$ > **Why this step?** Only the *difference* in $V_{GS}$ enters the exponent; $V_{th}$, $I_0$ cancel. A 180 mV deeper OFF-bias cuts leakage ~100×. > [!example] 3 — Temperature blows leakage up > $S \propto T$: going from 300 K to 360 K makes $S$ grow by factor $360/300=1.2$, so $S: 89.5\to107$ mV/dec. Worse, $I_0\propto V_T^2$ *and* $V_T$ in the exponent both rise, so leakage rises **super-linearly** with $T$. This is why hot chips leak more, heat up more → thermal runaway risk. --- ## Common mistakes > [!mistake] "Below threshold the current is exactly zero." > **Why it feels right:** we're taught $I_D = \tfrac12\mu C_{ox}\tfrac{W}{L}(V_{GS}-V_{th})^2$, which gives 0 (or imaginary) below $V_{th}$. > **The fix:** that square-law model is for *strong inversion only*. Below $V_{th}$ a **different, exponential** law governs. The transistor is a leaky, not perfect, switch. The square-law simply doesn't apply there. > [!mistake] "Subthreshold current depends strongly on $V_{DS}$." > **Why it feels right:** in saturation we expect $I_D$ tied to $V_{DS}$ via channel-length modulation. > **The fix:** $I_{sub}\propto(1-e^{-V_{DS}/V_T})$ **saturates** once $V_{DS}\gtrsim 3V_T\approx 78$ mV. The dominant control knob is $V_{GS}$ (exponentially), *not* $V_{DS}$. > [!mistake] "You can push $S$ below 60 mV/dec by better fabrication." > **Why it feels right:** better oxides make $C_{ox}$ big, $C_{dep}/C_{ox}\to 0$, $n\to 1$. > **The fix:** even at $n=1$ you hit $S=V_T\ln10=60$ mV/dec — set by $kT/q$. Fabrication gets you *toward* 60, never below (at room T). Breaking it needs a new transport mechanism (band-to-band tunneling in TFETs). --- ## #flashcards/hardware What region does subthreshold conduction occur in? ::: Weak inversion, $V_{GS}<V_{th}$, channel only weakly inverted. By what transport mechanism does subthreshold current flow? ::: Diffusion (like a BJT base), not drift. Write the subthreshold current formula. ::: $I_{sub}=I_0\,e^{(V_{GS}-V_{th})/nV_T}\,(1-e^{-V_{DS}/V_T})$. Define the subthreshold swing $S$. ::: $S=nV_T\ln 10$; mV of $V_{GS}$ to change $I_{sub}$ by 10×. What is the ideal room-temperature limit of $S$ and why? ::: 60 mV/decade, because $n\ge1$ and $S_{min}=(kT/q)\ln10$ (Boltzmann limit). What is the slope factor $n$? ::: $n=1+C_{dep}/C_{ox}$, the capacitive-divider factor; typically 1.1–1.5. Above what $V_{DS}$ does $I_{sub}$ saturate? ::: About $3V_T\approx78$ mV at 300 K. Why does leakage worsen with temperature? ::: $S\propto T$ and $V_T$ appears in exponent + $I_0\propto V_T^2$ → super-linear rise, risking thermal runaway. What is $V_T=kT/q$ at 300 K? ::: ≈ 25.9 mV. Does $V_{GS}$ or $V_{DS}$ dominate subthreshold current? ::: $V_{GS}$, exponentially; $V_{DS}$ only until ~78 mV then saturates. --- > [!recall]- Feynman: explain to a 12-year-old > Imagine a water tap you turned "off," but a thin thread of water still drips out. The harder you crank the handle toward closed, the *ten-times-smaller* the drip gets for each little extra turn — but it never fully stops. A transistor's "off" is like that leaky tap: it always drips a tiny current. With billions of taps on one chip, all those tiny drips add up to a real puddle of wasted battery. And a fundamental rule (from how heat jiggles the electrons) says each "10× smaller drip" costs you at least 60 millivolts of handle-turning — you can't do better at room temperature. > [!mnemonic] Remember it > **"Sixty is the floor, Volt-Thermal times ln-ten no more."** > $S=nV_T\ln10 \ge 60$ mV/dec. And **SUB = Slow, Under, Boltzmann**: **S**low exponential tail, **U**nder threshold, driven by **B**oltzmann statistics. ## Connections - [[MOSFET operating regions]] — subthreshold is the region *below* the square-law regime. - [[Threshold voltage Vth]] — the reference point of the exponential. - [[BJT diffusion current]] — same diffusion physics; MOSFET-in-weak-inversion ≈ BJT. - [[Thermal voltage kT-q]] — sets the 60 mV/dec Boltzmann limit. - [[Static vs dynamic power dissipation]] — leakage is the main static-power culprit. - [[Body effect]] — same capacitive divider gives both $n$ and $V_{th}$ shift. - [[Short-channel effects / DIBL]] — lowers effective $V_{th}$, boosting leakage. ## 🖼️ Concept Map ```mermaid flowchart TD OFF[MOSFET OFF, VGS below Vth] -->|leaks| ISUB[Subthreshold leakage Isub] WEAK[Weak inversion] -->|carriers move by| DIFF[Diffusion transport] DIFF -->|analogous to| BJT[BJT base diffusion] DIFF -->|gives| DIFFEQ[Isub = qADn dn/dx] BOLTZ[Boltzmann surface carriers] -->|n0 ~ exp qPsi/kT| EXP[Exponential in VGS] CDIV[Capacitive divider Cox and Cdep] -->|defines| NFACTOR[Slope factor n] NFACTOR -->|scales exponent| FORMULA[Isub = I0 exp of VGS-Vth over nVT] EXP -->|leads to| FORMULA DIFFEQ -->|combined with Boltzmann| FORMULA FORMULA -->|VDS above 3VT| SAT[Saturates in VDS] FORMULA -->|yields| SWING[Subthreshold swing S] ISUB -->|wastes| POWER[Static power in billions of transistors] ``` ## 🔊 Hinglish (regional understanding) > [!intuition]- Hinglish mein samjho > Dekho, MOSFET ko hum ek switch samajhte hain — ON matlab current flows, OFF matlab zero. Par reality mein OFF state (jab $V_{GS} < V_{th}$) mein bhi ek chhoti si current leak hoti rehti hai. Isko **subthreshold leakage current** kehte hain. Yeh current drift se nahi, balki **diffusion** se behti hai — bilkul BJT ke base jaisa. Aur sabse important baat: yeh $V_{GS}$ ke saath **exponential** roop se girti hai, dhang se zero nahi hoti. > > Formula yaad rakho: $I_{sub}=I_0\,e^{(V_{GS}-V_{th})/nV_T}$. Yahaan $V_T=kT/q\approx 26$ mV hai (thermal voltage), aur $n=1+C_{dep}/C_{ox}$ slope factor hai. Ab ek key quantity hai **subthreshold swing** $S = nV_T\ln 10$ — matlab current ko 10 guna kam karne ke liye kitna $V_{GS}$ ghatana padega. Room temperature pe iska **minimum 60 mV/decade** hai, chahe kitni bhi achhi fabrication karo. Isko "Boltzmann tyranny" kehte hain — physics ki deewaar hai. > > Yeh matter kyun karta hai? Aaj ke chips mein **billions** transistors hote hain. Har ek thoda thoda leak karega toh total **static power** bahut ban jaata hai — battery khaali, chip garam. Aur garam hone pe leakage aur badhta hai ($S\propto T$), jo ek dangerous feedback loop (thermal runaway) bana sakta hai. > > Toh exam aur real life dono ke liye yaad rakho: transistor kabhi perfectly OFF nahi hota, leakage exponential hoti hai, aur 60 mV/decade wall ko normal MOSFET tod nahi sakta. Isi wajah se supply voltage $V_{DD}$ ko bahut neeche nahi le ja sakte. ![[audio/2.4.17-Subthreshold-leakage-current.mp3]]