Process nodes (28nm→7nm→5nm→3nm→2nm)

WHAT is a process node?

WHY the number lost its physical meaning:

In the 1970s–2000s, "node" ≈ smallest gate length ≈ half-pitch. Everything shrank together (Dennard scaling).
Around 22nm, shrinking a flat (planar) transistor stopped working — leakage exploded. Makers changed the transistor shape (FinFET, then GAA) instead of only shrinking. The "nm" label kept dropping for marketing continuity even though gate length stalled around ~15–20nm.

WHY we shrink at all — the three drivers (PPA)

1. Area / density — the real metric

Derivation from scratch: a logic cell occupies width $w$ and height $h$ , both roughly set by pitch $p$ . Cell area $A=w\cdot h \propto p^2$ . Shrink every linear pitch by $k$ : $A_{\text{new}}=k^2 A_{\text{old}}$ . Number of cells in fixed die area = (die area)/ $A$ , so it multiplies by $1/k^2$ . A "0.7× linear shrink" per node gives $1/0.7^2 \approx 2\times$ density — the classic doubling behind Moore's Law.

2. Power — dynamic energy per switch

Derivation: charging a capacitor $C$ to voltage $V$ moves charge $Q=CV$ and stores energy $E=\tfrac12 CV^2$ . The same energy is dissipated discharging, so a full switch cycle dissipates $CV^2$ . Doing this $f$ times per second for a node switching a fraction $\alpha$ of the time gives $P_{\text{dyn}}=\alpha C V^2 f$ .

WHY nodes cut power: smaller transistors → smaller $C$ ; new nodes also lower $V$ . Since power depends on $V^2$ , dropping $V$ from 0.9 V to 0.7 V alone cuts dynamic energy by $(0.7/0.9)^2\approx 0.60$ — a 40% saving.

3. Leakage — the wall that killed planar transistors

HOW the transistor shape changed across nodes

Figure — Process nodes (28nm→7nm→5nm→3nm→2nm)

WHY more gate coverage helps: the gate's job is to switch the channel on/off. More surrounding surface = stronger electric field control = the transistor turns fully OFF (low leakage) and fully ON (high current) even when very short.

Node	Year (~)	Architecture	Notable
28nm	2011	Planar	last "long-lived" cheap planar
14/16nm	2014	FinFET	first FinFET volume
7nm	2018	FinFET	first EUV use (7nm+/N7)
5nm	2020	FinFET	EUV mainstream
3nm	2022–23	FinFET (TSMC N3) / GAA (Samsung)	mixed
2nm	2025+	GAA nanosheet	+ backside power delivery

Worked examples

Common mistakes (steel-manned)

Flashcards

What does the "nm" in a modern process node name actually represent?

A marketing/generation label, decoupled from any single physical transistor dimension (gate length is still ~15–20nm at "3nm").

Which physical quantity historically equalled the node number?

The half-pitch (half the spacing between repeated metal lines).

State the dynamic power formula and derive the

V^2

term.

P_{dyn}=\alpha C V^2 f

; charging

C

V

stores

\tfrac12CV^2

, discharging dissipates the same, so a full cycle dissipates

CV^2

Why did Dennard scaling break down around 2005?

Voltage couldn't keep dropping because lowering

V_{th}

raises subthreshold leakage exponentially (

I_{leak}\propto e^{-qV_{th}/nkT}

), so power density rose.

How does density scale with a linear shrink factor

k

D_{new}=D_{old}/k^2

(area is 2-D), so

k=0.7

≈ 2× density.

Order the transistor architectures by node era.

Planar (≥28nm) → FinFET (22nm–7nm) → GAA/nanosheet (3nm,2nm).

Why does gate-all-around beat FinFET?

Gate wraps channel on all 4 sides → strongest electrostatic control → lower leakage at short lengths.

What is EUV and why needed at ~7nm?

Extreme-UV lithography at 13.5nm wavelength; prints fine features in single exposure instead of slow multi-patterning.

Is a smaller node necessarily a faster clock?

No — clocks plateaued ~3–5GHz; smaller nodes give density & efficiency, not much higher

f

What single metric best compares nodes across companies?

Transistor density (MTr/mm²), since node names aren't standardized.

Recall Feynman: explain to a 12-year-old

Imagine building a city of tiny light-switches. "28nm" and "3nm" are just the names of newer city-building recipes, like "2011 recipe" vs "2023 recipe." Newer recipes let you pack way more switches into the same land, and each switch uses less battery. But the switches got so small that a flat switch started "leaking" electricity even when off — so engineers changed the switch's shape, wrapping the control finger all the way around it (like holding a straw with your whole fist instead of one finger) so it turns off properly. The name keeps shrinking for marketing, but nothing on the chip is really "3 nanometres" wide.

Connections

FinFET and GAA transistors
Dennard scaling and Moore's Law
EUV Lithography
Subthreshold leakage / MOSFET threshold voltage
Dynamic vs static power
Backside power delivery (2nm era)
CMOS fabrication steps

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, "process node" ka matlab log samajhte hain ki chip pe kuch cheez literally 3 nanometre wide hai — par aisa nahi hai. Aaj kal "28nm", "7nm", "3nm" sirf ek generation ka naam hai, marketing label, jaise "2011 model" vs "2023 model". Purane time mein number sach mein half-pitch ke barabar hota tha, par ab gate length "3nm" node pe bhi ~16-20nm hoti hai. Toh number chhota hone ka asli matlab hai: zyada transistors per mm² (density), kam power per switch, aur thodi better speed — isko PPA (Power, Performance, Area) bolte hain.

Density kyun double hoti hai har node pe? Kyunki agar tum har linear dimension ko $k$ (jaise 0.7) se chhota karo, area 2-D hai toh $k^2$ se chhoti hoti hai — matlab $1/0.7^2 \approx 2\times$ zyada transistors. Power kam hoti hai kyunki $P_{dyn}=\alpha C V^2 f$ ; voltage $V$ thoda giraya toh $V^2$ ki wajah se bada saving milta hai.

Ek badi baat: 2005 ke aas-paas Dennard scaling toot gayi. Voltage ko aur neeche nahi le ja sakte kyunki $V_{th}$ girao toh leakage exponentially badhti hai ( $I_{leak}\propto e^{-qV_{th}/nkT}$ ). Isiliye engineers ne transistor ki shape badli — flat (planar) se FinFET (gate 3 taraf se wraps) aur ab GAA nanosheet (charo taraf se wraps). Zyada gate coverage = better on/off control = kam leakage. Saath mein EUV lithography (13.5nm light) aayi taaki chhoti features print ho saken.

Exam/interview ke liye yaad rakho: node ka naam standardized nahi hai (Intel ka 10nm ≈ TSMC ka 7nm), toh companies compare karne ke liye MTr/mm² dekho, naam nahi. Aur chhota node ka matlab tez clock nahi — clocks 3-5 GHz pe stuck hain kyunki heat nikaalna mushkil hai; chhota node ka fayda density aur efficiency hai.

Process nodes (28nm→7nm→5nm→3nm→2nm)

WHAT is a process node?

WHY we shrink at all — the three drivers (PPA)

1. Area / density — the real metric

2. Power — dynamic energy per switch

3. Leakage — the wall that killed planar transistors

HOW the transistor shape changed across nodes

Worked examples

Common mistakes (steel-manned)

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Semiconductor Fabrication

Connections