Noesis
4.3.17Semiconductor Fabrication

Copper damascene process

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🇮🇳 Yeh note Hinglish mein padho →

WHY does this process exist?

WHY copper instead of aluminum?

  • Copper resistivity ρCu≈1.68 μΩ⋅cm\rho_{Cu}\approx 1.68\ \mu\Omega\cdot\text{cm} vs aluminum ρAl≈2.65 μΩ⋅cm\rho_{Al}\approx 2.65\ \mu\Omega\cdot\text{cm} → ~40% lower → less RC delay, faster chips.
  • Copper resists electromigration far better (higher activation energy) → more reliable at high current density.

WHY not just etch copper like aluminum?

  • Aluminum is patterned by reactive ion etching (RIE): you deposit a metal blanket, mask it, and etch away the unwanted metal because Al forms volatile chlorides (AlCl3\text{AlCl}_3 boils off).
  • Copper halides (CuCl\text{CuCl}, CuF2\text{CuF}_2) are NOT volatile at reasonable temperatures → you can't just etch them off as gas. So subtractive etching fails.
  • Fix (the whole point of damascene): turn the problem inside-out — etch the dielectric (SiO₂ / low-k), which etches easily, then inlay copper.

WHAT are the two flavours?

Dual damascene is the industry standard for modern back-end-of-line (BEOL).

HOW: the dual damascene flow, step by step

Figure — Copper damascene process
  1. Deposit dielectric (SiO₂ or low-k) on the wafer over the lower metal. Why? This is the material we will carve the wire shape into.
  2. Etch via + trench into the dielectric using photolithography + RIE (two lithography masks: one for via, one for trench). Why RIE works here: SiO₂ etches into volatile fluorides (SiF4\text{SiF}_4) — easy, unlike copper.
  3. Deposit barrier layer (Ta / TaN, ~a few nm) conformally lining the trench. Why? Copper diffuses fast into silicon and SiO₂, poisoning transistors (deep-level traps). The barrier blocks Cu diffusion and improves adhesion.
  4. Deposit copper seed layer (thin PVD Cu). Why? Electroplating needs a conductive starting surface to carry current.
  5. Electroplate (ECD) copper to overfill the trench + via (bottom-up superfill). Why overfill? Guarantees no voids inside the trench; excess is removed next.
  6. CMP (Chemical Mechanical Polish) to remove the copper overburden and barrier down to the dielectric surface — leaving copper only inside the trenches. Why? This planarizes the surface so the next layer can be built flat (essential for lithography depth-of-focus).
  7. Deposit capping layer (e.g. SiN, SiCN) on top. Why? Copper's top surface is exposed after CMP; the cap prevents Cu oxidation/diffusion upward and blocks electromigration along the top interface.
  8. Repeat for the next metal level.

The physics that MOTIVATES it — deriving RC delay

Recall

Recall Active recall — cover the answers
  • Why can't copper be subtractively etched like aluminum? → its halides are non-volatile
  • Where is the wire pattern defined in damascene? → in the dielectric, not the metal
  • What is deposited between copper and dielectric, and why? → Ta/TaN barrier to stop Cu diffusion
  • What does "dual" mean in dual damascene? → via + trench filled in one copper step
  • What removes the copper overburden? → CMP
  • Why copper over aluminum? → lower resistivity (~37% less RC) + better electromigration
Recall Feynman: explain to a 12-year-old

Imagine you want gold vines on a knife. You can't melt gold onto the surface and cut away the wrong bits — the gold smears. So instead you carve grooves shaped like vines into the steel, pour molten gold into the grooves, and then sand the top flat until gold shows only inside the grooves. Computer chips do exactly this: they carve tiny wire-shaped ditches in glass, fill them with copper, and sand the top smooth. They even line the ditches with a thin "raincoat" (barrier) so the copper doesn't leak into the glass and ruin things.

Flashcards

Why is copper patterned by damascene instead of subtractive etch?
Copper halide etch byproducts are non-volatile, so copper can't be dry-etched cleanly; damascene inlays copper into pre-etched dielectric trenches instead.
In damascene, which material carries the wire pattern?
The dielectric (insulator) — trenches etched into it define the wires.
What is dual damascene?
A process where the via and the trench above it are both etched into the dielectric and filled with copper in a single metal-deposition step.
Purpose of the Ta/TaN barrier layer?
To block copper diffusion into the dielectric/silicon and improve adhesion.
Why a copper seed layer before electroplating?
Electroplating needs a conductive surface to start current flow for bottom-up copper fill.
What does CMP do in damascene?
Removes copper overburden and barrier down to the dielectric, leaving copper only in trenches, and planarizes the surface for the next layer.
Why copper over aluminum for interconnects?
Lower resistivity (1.68 vs 2.65 µΩ·cm → ~37% lower RC delay) and better electromigration resistance.
Formula for interconnect resistance?
R = ρL/(w·t).
How does RC delay scale with wire length?
As L² — long global wires dominate delay.
Why a capping layer on top of the copper after CMP?
To prevent Cu oxidation/upward diffusion and suppress electromigration along the top interface.

Connections

  • Chemical Mechanical Polishing (CMP)
  • Reactive Ion Etching
  • Low-k dielectrics
  • Electromigration
  • Back-End-Of-Line (BEOL)
  • Photolithography
  • RC delay in interconnects
  • Aluminum metallization (subtractive)

Concept Map

lower resistivity, less RC delay

better electromigration

subtractive RIE etch fails

solution

pattern etched into dielectric

SiO2 etches to volatile SiF4

two variants

via plus trench in one fill

BEOL standard

line trench first

blocks Cu diffusion into Si

planarize excess

Copper wires needed

Cu beats Al

Cu halides not volatile

Cannot etch copper

Damascene process

Etch via plus trench

RIE works on dielectric

Single vs Dual damascene

Dual damascene

Fewer CMP steps

Deposit barrier Ta/TaN

Fill copper

CMP polish

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, problem ye hai ki copper ko aluminum ki tarah seedha etch nahi kar sakte. Aluminum ka etch karo toh uske chloride gas ban ke ud jaate hain, par copper ke halides volatile nahi hote — wo chipak jaate hain aur mess kar dete hain. Isliye engineers ne ulta trick lagaya: pehle insulator (dielectric) mein wire ke shape ki khaai (trench) khod lo, phir usme copper bhar do, aur upar ka extra copper CMP se ghis ke flat kar do. Bas copper sirf trench ke andar reh jaata hai. Isi ko damascene bolte hain — naam Damascus ki purani gold-inlay art se aaya hai.

Dual damascene ka matlab hai via (vertical connection) aur trench (horizontal wire) dono ek hi copper fill mein bhar do — steps kam, sasta, reliable. Beech mein ek patli barrier layer (Ta/TaN) lagate hain kyunki copper silicon aur SiO2 mein tezi se diffuse ho jaata hai aur transistor kharab kar deta hai — barrier raincoat ki tarah use rokta hai. Phir seed layer, electroplating se fill, CMP se polish, aur upar cap layer.

Ye sab kyun? Kyunki copper ki resistivity aluminum se ~37% kam hai (1.68 vs 2.65 µΩ·cm), toh RC delay kam hoti hai aur chip fast chalta hai. Yaad rakho: RC∝ρεrL2/(ws)RC \propto \rho \varepsilon_r L^2/(w s) — lambi wires (L2L^2) sabse zyada delay deti hain, aur ρ\rho kam karne se (copper) turant fayda. Isliye modern chips ka BEOL pura copper damascene par chalta hai.

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Connections

Chemical mechanical planarization (CMP)Hardware · 4.3.15Chemical mechanical planarization (CMP)Hardware · 4.3.15Electromigration reliabilityHardware · 6.4.8