Level 1 — RecognitionSemiconductor Fabrication

Semiconductor Fabrication

⏱ 20 minutes30 marksprintable — key stays hidden on paper

Chapter: 4.3 Semiconductor Fabrication Level: 1 — Recognition (MCQ + Matching + True/False with justification) Time Limit: 20 minutes Total Marks: 30

Section A — Multiple Choice (1 mark each; 10 marks)

Q1. The Czochralski process is used to produce:

(a) Photoresist films
(b) Single-crystal silicon ingots
(c) Copper interconnects
(d) Plasma etch gases

Q2. In a positive photoresist, the regions exposed to UV light become:

(a) Insoluble in developer
(b) Soluble in developer
(c) Electrically conductive
(d) Permanently hardened

Q3. The wavelength associated with EUV lithography is approximately:

(a) 193 nm
(b) 248 nm
(c) 13.5 nm
(d) 365 nm

Q4. Which process grows a layer of $SiO_2$ by reacting silicon with oxygen at high temperature?

(a) Sputtering
(b) Thermal oxidation
(c) Ion implantation
(d) CMP

Q5. Dry (plasma) etching is generally preferred over wet etching because it is more:

(a) Isotropic
(b) Anisotropic (directional)
(c) Chemically selective only
(d) Suitable for cleaning

Q6. Atomic Layer Deposition (ALD) is distinguished by:

(a) Self-limiting single-atomic-layer growth per cycle
(b) Bulk melting of silicon
(c) Mechanical polishing
(d) Directional ion bombardment

Q7. The copper damascene process differs from traditional aluminium metallization because copper is:

(a) Etched directly into patterns
(b) Deposited into etched trenches then planarized
(c) Evaporated only
(d) Grown by oxidation

Q8. A FinFET improves on the planar transistor by:

(a) Removing the gate entirely
(b) Wrapping the gate around a raised fin channel on multiple sides
(c) Using copper as the channel
(d) Eliminating the need for a substrate

Q9. Chemical Mechanical Planarization (CMP) is used to:

(a) Dope the wafer
(b) Flatten/planarize the wafer surface
(c) Cut the ingot into wafers
(d) Bond wires to the package

Q10. Flip-chip packaging connects the die to the substrate using:

(a) Long gold wire bonds only
(b) Solder bumps on the die face
(c) Epoxy adhesive alone
(d) A Czochralski seed crystal

Section B — Matching (1 mark each; 8 marks)

Q11–Q18. Match each process/term (left) to its correct description (right). Write the letter.

#	Term		Description
Q11	Photolithography	A	Adds dopant atoms by accelerating ions into the wafer
Q12	Ion implantation	B	Depositing thin films from a gas-phase chemical reaction
Q13	CVD	C	Transfers a mask pattern into photoresist using light
Q14	PVD / sputtering	D	Gate wraps completely around stacked nanosheet channels
Q15	GAA nanosheet	E	Ejecting target atoms with ions to coat the wafer
Q16	Reticle	F	Defects per unit area used to predict good dies
Q17	Defect density	G	Sorting chips by performance/quality after test
Q18	Binning	H	Photomask carrying the pattern for a projection stepper

Section C — True/False with justification (2 marks each; 12 marks)

(1 mark correct T/F, 1 mark for a correct one-line justification.)

Q19. EUV lithography needs fewer multi-patterning steps than 193 nm DUV for the same fine feature. (T/F + justify)

Q20. Smaller process nodes (e.g., 3 nm vs 28 nm) always correspond to a physical gate length exactly equal to the node number. (T/F + justify)

Q21. Negative photoresist becomes soluble where it is exposed to light. (T/F + justify)

Q22. Ion implantation is usually followed by an annealing step. (T/F + justify)

Q23. Wafer cleaning (e.g., RCA clean) is performed to remove particles, organics, and metal contamination before high-temperature steps. (T/F + justify)

Q24. A higher defect density on a wafer increases the yield of good dies. (T/F + justify)

Answer keyMark scheme & solutions

Section A (1 mark each)

Q1. (b) Single-crystal silicon ingots. Czochralski pulls a seed crystal from molten silicon to grow a cylindrical monocrystal ingot. (1)

Q2. (b) Soluble in developer. In positive resist, exposure breaks polymer bonds, so exposed regions dissolve away. (1)

Q3. (c) 13.5 nm. EUV uses 13.5 nm radiation, far shorter than DUV's 193 nm. (1)

Q4. (b) Thermal oxidation. Si + O reacts at high T to grow $SiO_2$ . (1)

Q5. (b) Anisotropic (directional). Plasma etching gives vertical, directional profiles needed for fine features. (1)

Q6. (a) Self-limiting single-atomic-layer growth per cycle. ALD uses sequential self-limiting surface reactions for atomic-scale thickness control. (1)

Q7. (b) Deposited into etched trenches then planarized. Copper is hard to etch, so damascene fills pre-etched trenches then CMP removes excess. (1)

Q8. (b) Wrapping the gate around a raised fin on multiple sides. 3D fin gives better electrostatic gate control. (1)

Q9. (b) Flatten/planarize the wafer surface. CMP combines chemical slurry + mechanical polishing. (1)

Q10. (b) Solder bumps on the die face. Flip-chip flips the die and bonds via solder bumps. (1)

Section B (1 mark each)

Q	Answer
Q11	C — pattern transfer using light
Q12	A — doping by accelerated ions
Q13	B — film from gas-phase reaction
Q14	E — sputtering ejects target atoms
Q15	D — gate around stacked nanosheets
Q16	H — photomask for projection stepper
Q17	F — defects per unit area
Q18	G — sorting chips by quality

Section C (2 marks each: 1 T/F + 1 justification)

Q19. TRUE. EUV's short 13.5 nm wavelength resolves fine features in a single exposure, avoiding the double/quadruple patterning DUV needs. (1+1)

Q20. FALSE. Node names (3 nm, 5 nm) are marketing/scaling labels, not the actual physical gate length, which is larger. (1+1)

Q21. FALSE. Negative resist becomes INSOLUBLE (crosslinks/hardens) where exposed; unexposed areas wash away. (1+1)

Q22. TRUE. Annealing repairs lattice damage from implantation and electrically activates the dopants. (1+1)

Q23. TRUE. Contaminants cause defects and diffuse into the wafer at high temperature, so cleaning precedes oxidation/diffusion. (1+1)

Q24. FALSE. More defects mean more dies contain killer faults, so good-die yield DECREASES. (1+1)

[
  {"claim":"EUV wavelength 13.5 nm is much smaller than DUV 193 nm",
   "code":"euv=13.5; duv=193; result = euv < duv"},
  {"claim":"Poisson yield falls as defect density rises (Q24 direction)",
   "code":"from sympy import exp; A=1.0; D_low=0.1; D_high=0.5; Y_low=exp(-A*D_low); Y_high=exp(-A*D_high); result = Y_high < Y_low"},
  {"claim":"Node label (3 nm) is not equal to a realistic physical gate length (~16-18 nm)",
   "code":"node=3; gate_length=16; result = node != gate_length"},
  {"claim":"ALD deposits roughly one atomic layer (~0.1 nm) per cycle, so 100 cycles ~ 10 nm",
   "code":"per_cycle=0.1; cycles=100; thickness=per_cycle*cycles; result = abs(thickness-10) < 1e-9"}
]