Exercises — Copper damascene process

The wire pattern is defined in the dielectric (the insulator) — trenches are carved into it and then filled with metal. Copper cannot be subtractively etched because its halides (CuCl, CuF₂) are not volatile at reasonable temperatures, so the etch byproducts will not fly off as gas; they redeposit and corrode. See Reactive Ion Etching and Aluminum metallization (subtractive) for the contrast.

Correct order (mnemonic "Dig, Line, Seed, Fill, Polish, Cap"):

1. Etch trench+via (Dig)
2. Barrier deposit, e.g. Ta/TaN (Line)
3. Seed copper layer (Seed)
4. Fill — electroplate copper (Fill)
5. CMP (Polish) — see Chemical Mechanical Polishing (CMP)
6. Cap layer, e.g. SiN/SiCN (Cap)

CMP (Chemical Mechanical Polishing). It grinds away the copper overburden and barrier down to the dielectric top, so copper survives only inside the trenches — that leftover copper is the wire.

WHAT: use $R=\rho \frac{L}{A}$ with $A=wt$. WHY this formula: current runs along $L$ and spreads across $A$; more length = longer path = more $R$, more area = less crowding = less $R$. Convert to SI first (this is where marks are lost): $L=500\times 10^{-6}\text{m}=5\times 10^{-4}\text{m}$ $A=(0.10\times 10^{-6})(0.25\times 10^{-6})=2.5\times 10^{-14}{\text{m}}^2$ $R=\frac{1.68\times 10^{-8}\times 5\times 10^{-4}}{2.5\times 10^{-14}}=\frac{8.4\times 10^{-12}}{2.5\times 10^{-14}}=336\Omega$

WHY parallel-plate: the two facing sidewalls act as capacitor plates of area $t\times L$, separated by the gap $s$ filled with dielectric. $tL=(0.25\times 10^{-6})(5\times 10^{-4})=1.25\times 10^{-10}{\text{m}}^2$ $C=4.0\times (8.854\times 10^{-12})\times \frac{1.25\times 10^{-10}}{0.10\times 10^{-6}}$ $C=4.0\times 8.854\times 10^{-12}\times 1.25\times 10^{-3}=4.43\times 10^{-14}\text{F}\approx 44.3\text{fF}$

WHY $t$ cancels: $R\propto 1/t$ but $C\propto t$; multiply and $t$ disappears — thickness trades resistance against capacitance, it cannot help the product. $\frac{L^2}{ws}=\frac{(5\times 10^{-4}{)}^2}{(0.10\times 10^{-6})(0.10\times 10^{-6})}=\frac{2.5\times 10^{-7}}{1.0\times 10^{-14}}=2.5\times 10^7$ $RC=(1.68\times 10^{-8})(4.0)(8.854\times 10^{-12})(2.5\times 10^7)$ $RC=1.68\times 10^{-8}\times 3.5416\times 10^{-11}\times 2.5\times 10^7\approx 1.488\times 10^{-11}\text{s}\approx 14.9\text{ps}$ (Check: $R\times C=336\times 4.43\times 10^{-14}=1.49\times 10^{-11}$ s ✓ — the two independent routes agree.)

WHY only the ratio survives: $L,w,s,{\epsilon }_r$ are identical, so in $RC=\rho {\epsilon }_r{\epsilon }_0\frac{L^2}{ws}$ every factor except $\rho$ cancels in the ratio. $\frac{R{C}_{Cu}}{R{C}_{Al}}=\frac{{\rho }_{Cu}}{{\rho }_{Al}}=\frac{1.68}{2.65}=0.634$ So copper's delay is $63.4\%$ of aluminum's → a reduction of $1-0.634=0.366\approx 37\%$. This ~37% is the whole commercial reason for the switch. See RC delay in interconnects.

WHY multiply the two ratios: $RC\propto \rho \cdot {\epsilon }_r$, and the two changes are independent factors. $\frac{R{C}_{new}}{R{C}_{old}}=\frac{{\rho }_{Cu}}{{\rho }_{Al}}\cdot \frac{{\epsilon }_{r,\text{low-k}}}{{\epsilon }_{r,{\text{SiO}}_2}}=0.634\times \frac{2.5}{4.0}=0.634\times 0.625=0.396$ New delay is $\approx 39.6\%$ of old → about a $60\%$ reduction. Damascene is the enabling process for both changes at once (it makes copper fillable and is compatible with fragile low-k films).

WHAT: the barrier steals $b$ from each side, so it removes $2b$ from the width. $w_{Cu}=w-2b=0.10-2(0.015)=0.10-0.030=0.070\mu \text{m}$ Fraction of copper $=\frac{w_{Cu}}{w}=\frac{0.070}{0.10}=0.70=70\%$. Consequence: the true copper resistance is higher than the naive $R=\rho L/(wt)$ suggests, because $A$ shrinks. As wires get narrower, this barrier "tax" gets worse — that's why research pushes for thinner barriers (see the parent's steel-man).

WHY compare factors: hold everything else fixed and look at the multiplier on $RC$.

• Halving $L$: $RC\to RC\times (1/2{)}^2=0.25RC$ → a 75% reduction.
• Al→Cu: $RC\to RC\times 0.634$ → a 37% reduction. Halving the length wins by a landslide, because delay scales with $L^2$ (quadratic) while the metal switch is only a linear factor in $\rho$. Synthesis lesson: architecture (short wires) beats materials — but you usually can't freely shorten wires, so in practice you do both. Damascene enables the metal half.

After CMP the copper's top surface is bare. Three linked reasons the cap is critical:

1. Electromigration: metal atoms drift under high current density; the fastest diffusion path is along a free surface/interface. A bare copper top is a superhighway for atom migration → voids → open circuits. The cap pins the top interface raising the activation energy for migration.
2. Diffusion/oxidation: exposed copper oxidises and can diffuse upward into the next dielectric, poisoning it — the cap seals it, acting as the top barrier (the Ta/TaN only lines sides+bottom).
3. BEOL stacking: in Back-End-Of-Line (BEOL) you build level upon level; each cap becomes the etch-stop and diffusion seal for the next damascene cycle. It matters most in the lowest, thinnest metal levels (highest current density, tightest pitch).

1. Fewer CMP steps → cheaper & higher yield. Each CMP is expensive and slightly damages the surface; one fill means one polish instead of two. See Chemical Mechanical Polishing (CMP).
2. Fewer copper–copper interfaces → lower resistance & better reliability. Single damascene leaves a via/line boundary (an interface with barrier residue and a resistance bump, plus an electromigration weak spot). Dual damascene makes via+line a single continuous copper body — one grain structure, no buried interface.

The tempting arithmetic: from L3.3, removing a $2b=0.03\mu \text{m}$ barrier restores width $0.070\to 0.100\mu \text{m}$, i.e. area $\times \frac{0.100}{0.070}=1.43$, so $R$ drops by $1-1/1.43=30\%$. Genuinely attractive on paper. Why it is fatal anyway: copper diffuses fast into SiO₂ and silicon. Within a single thermal cycle (~$400^{\circ }\text{C}$ BEOL anneal) copper penetrates the dielectric, creating deep-level traps and leakage paths that destroy nearby transistors — a catastrophic, non-recoverable failure, not a performance tweak. See Electromigration and the diffusion note in the parent. Verdict: No. The 30% resistance win is real but irrelevant if the chip does not function. Correct engineering direction: keep the barrier but make it thinner / higher-quality (e.g. thinner TaN or self-forming barriers), pursuing the same area back without opening a diffusion path.

WHY: the conducting copper width is only $w_{Cu}=w-2b=0.070\mu \text{m}$ (L3.3), so the real area is smaller. $A_{real}=w_{Cu}t=(0.070\times 10^{-6})(0.25\times 10^{-6})=1.75\times 10^{-14}{\text{m}}^2$ $R_{real}=\frac{\rho L}{A_{real}}=\frac{(1.68\times 10^{-8})(5\times 10^{-4})}{1.75\times 10^{-14}}=\frac{8.4\times 10^{-12}}{1.75\times 10^{-14}}=480\Omega$ Ideal from L2.1 was $336\Omega$. So the barrier tax raises resistance by $\frac{480}{336}=1.43\Rightarrow +43\%.$ Mastery takeaway: the datasheet ($336\Omega$) is optimistic; the manufacturable wire is $\sim 43\%$ worse because a real trench must be lined. This gap is exactly what drives barrier-thinning research — and it is why you can never omit the barrier (L5.1) even though it hurts $R$.

• Which formula gives wire resistance? ::: $R=\rho L/(wt)$
• In $RC=\rho {\epsilon }_r{\epsilon }_0{L}^2/(ws)$, which parameter cancelled and why? ::: thickness $t$ cancels, since $R\propto 1/t$ but $C\propto t$
• Copper vs aluminum delay ratio? ::: $1.68/2.65\approx 0.63$, i.e. ~37% faster
• Barrier on both sidewalls removes how much width? ::: $2b$
• Why never omit the barrier despite the resistance win? ::: copper diffuses into SiO₂/Si and kills transistors