Copper damascene process: Question bank — Hardware deep dive

First, meet the geometry (so no symbol is a stranger)

Before any question uses $w$ , $t$ , $s$ , $ρ$ , $ε_{r}$ or $ε_{0}$ , look at one copper wire and its neighbour in cross-section:

Definition The six symbols this page uses

$L$ :: length of the wire — how far the signal travels along it (into the page in the figure). Units: metres.
$w$ :: width of the trench/wire, measured across the top. Units: metres.
$t$ :: thickness (height) of the wire — how deep the trench is. Units: metres.
$s$ :: spacing — the gap of dielectric between one wire and its neighbour. Units: metres.
$ρ$ :: resistivity of the wire metal — how strongly the material itself opposes current, independent of shape. Units: ohm·metres ( $Ω \cdot m$ ). Copper's $ρ_{C u} \approx 1.68 \times 1 0^{- 8} Ω \cdot m$ ; aluminum's is higher.
$ε_{0}$ :: the permittivity of free space, a fixed constant of nature, $ε_{0} \approx 8.85 \times 1 0^{- 12} F/m$ (farads per metre). It sets how much capacitance any gap holds in vacuum.
$ε_{r}$ :: the relative permittivity (the "k" in low-k), a dimensionless number telling how much more charge the real dielectric stores than vacuum ( $ε_{r} \approx 3.9$ for SiO₂, lower for low-k).

True or false — justify

TF-1. "Damascene defines the wire pattern inside the copper itself."

False. The pattern is carved into the dielectric; copper merely fills the pre-shaped trench. The metal never carries the pattern.

TF-2. "Copper is used because it is cheaper than aluminum."

False. Copper is used for lower resistivity (~37% less RC delay) and better electromigration resistance — not cost; the process is actually more complex.

TF-3. "Subtractive RIE works for aluminum because

AlCl_{3}

boils off."

True. Aluminum chloride is volatile, so the etch byproduct leaves as gas. Copper halides are non-volatile, so the same trick fails — that is the whole reason damascene exists.

TF-4. "In dual damascene the via and the trench are filled in one copper deposition."

True. That single fill (plus one CMP) is precisely what "dual" means — fewer interfaces and fewer polish steps than single damascene.

TF-5. "The Ta/TaN barrier can be dropped to lower total resistance."

False. Without it copper diffuses into SiO₂/silicon in one thermal cycle, creating deep-level traps that poison transistors. Barriers get thinner, never zero.

TF-6. "CMP is a cosmetic polishing step."

False. CMP defines the wire by removing the copper overburden so metal remains only in the trenches, and it planarizes the surface for the next lithography depth-of-focus.

TF-7. "Lowering the dielectric constant lowers the wire's resistance."

False. Low-k lowers the relative permittivity

ε_{r}

, which shrinks the capacitance

C

, not resistance

R

R

is set by resistivity and geometry (

ρ L / (w t)

);

C

is set by the dielectric between wires.

TF-8. "In the

R C \propto ρ ε_{r} ε_{0} L^{2} / (w s)

result, making wires shorter helps a lot."

True. Recall

R C = ρ \frac{L}{w t} \cdot ε_{r} ε_{0} \frac{t L}{s} = ρ ε_{r} ε_{0} \frac{L ^{2}}{w s}

(the

t

's cancelled). Delay scales as

L^{2}

, so halving a wire's length cuts its RC delay to a quarter — long global wires are the true bottleneck.

TF-9. "The capping layer (SiN/SiCN) is deposited before electroplating."

False. The cap goes on after CMP, once the copper top is exposed, to stop oxidation and block electromigration along the top interface.

TF-10. "The seed layer and the plated bulk copper are deposited by the same method."

False. The seed is thin PVD copper to make the surface conductive; the bulk is grown by electroplating (ECD), which needs that conductive seed to carry current.

Spot the error

SE-1. "We etch the copper blanket with a fluorine plasma, forming

CuF_{2}

gas that floats away."

Error:

CuF_{2}

is non-volatile — it does not become gas at reasonable temperatures. It redeposits and corrodes sidewalls, which is why copper is never dry-etched.

SE-2. "Barrier → carve dielectric → fill copper → seed → CMP → cap."

Wrong order. Correct: carve dielectric → barrier → seed → fill → CMP → cap. Seed must come after the barrier and before plating (mnemonic: Dig, Line, Seed, Fill, Polish, Cap).

SE-3. "We overfill the trench with copper because thicker wires are less resistive."

Error: overfill guarantees the trench has no voids; the excess (overburden) is entirely removed by CMP, so it never adds to the final wire.

SE-4. "For a copper line of width

w = 0.1 μ m

and thickness

t = 0.2 μ m

, the cross-section is

A = w t = 0.1 \times 0.2 = 0.02 μ m^{2}

, so

R = 1.68 \times 1 0^{- 8} \times 1 0^{- 3} /0.02

Error: the area was not converted to SI. Here

0.1

and

0.2

are the width

w

and thickness

t

;

A = 0.02 μ m^{2} = 2 \times 1 0^{- 14} m^{2}

. Forgetting the

1 0^{- 12}

throws the answer off by

1 0^{12}

(correct

R = 840 Ω

SE-5. "Dual damascene needs only one lithography mask because via and trench are one step."

Error: filling is one step, but patterning still needs two masks — one for the via and one for the trench. "Dual" refers to the shared fill, not shared lithography.

SE-6. "Copper diffuses into silicon, so we grow a thick barrier to raise the wire resistance and slow the copper."

Error: we want the barrier thin. It blocks diffusion by chemistry (Ta/TaN), not by being thick; a thick barrier steals cross-section from the low-resistivity copper.

Why questions

WHY-1. Why can aluminum be subtractively etched but copper cannot?

Because aluminum's etch byproducts (chlorides) are volatile and leave as gas, while copper's halides are non-volatile — they cling, redeposit, and corrode instead of clearing.

WHY-2. Why carve the pattern into the dielectric instead of the metal?

Because SiO₂/low-k etches cleanly into volatile fluorides (

SiF_{4}

), so the dielectric is the etchable material — copper only needs depositing and polishing, sidestepping the un-etchable metal.

WHY-3. Why does the wire thickness

t

cancel in the RC-delay expression?

R = ρ L / (w t)

the

t

is in the denominator; in

C = ε_{r} ε_{0} t L / s

it is in the numerator. A thicker wire lowers

R

(bigger cross-section) but raises

C

(taller sidewall plates) by the same factor — the two effects cancel, so

t

trades

R

against

C

with no net delay change.

WHY-4. Why is a conductive seed layer needed before electroplating?

Electroplating drives ions to a surface by passing current through it; a bare insulator trench cannot carry that current, so a thin conductive copper seed is laid first.

WHY-5. Why does damascene enable both the copper and the low-k benefits at once?

Damascene lets you use copper (impossible to subtractively etch) and fragile low-k dielectrics (which cannot survive metal-etch plasmas), because it etches the dielectric and only inlays metal.

WHY-6. Why does CMP matter for the next layer, not just this one?

An un-planarized surface has hills and valleys; the next lithography step has a shallow depth-of-focus and cannot image sharp features over uneven topography — flatness is a hard requirement upward.

WHY-7. Why cap the copper on top after CMP rather than leave it bare?

The freshly polished copper top is exposed metal; without a cap it oxidizes, and the top interface becomes the fastest electromigration path — the cap seals both problems.

Edge cases

EC-1. What if a wire has zero length (

L = 0

Both

R

and

C

go to zero, and

R C \propto L^{2} \to 0

— a zero-length "wire" is just a contact point with no distributed delay.

EC-2. What if the two adjacent wires' spacing

s \to 0

C = ε_{r} ε_{0} t L / s

(with

ε_{0} \approx 8.85 \times 1 0^{- 12} F/m

the vacuum permittivity and

ε_{r}

the dielectric's relative permittivity), letting

s \to 0

sends

C \to \infty

; the parallel-plate model blows up, warning that tightly packed wires suffer the worst capacitive coupling and delay.

EC-3. What if the wire width

w \to 0

R = ρ L / (w t)

the width sits in the denominator, so

w \to 0

sends

R \to \infty

and hence

R C \propto ρ ε_{r} ε_{0} L^{2} / (w s) \to \infty

. A vanishingly thin wire has almost no cross-section to carry current — this is why aggressive width scaling raises resistance and eventually dominates delay.

EC-4. What if you used aluminum but kept the damascene flow?

It works but wastes the process — aluminum is subtractively etchable, so damascene's complexity buys you nothing; you'd get higher resistivity (

ρ_{A l} > ρ_{C u}

) with the same step count.

EC-5. What is the limiting behaviour of RC delay as wires are scaled longer for global routing?

Delay rises as

L^{2}

, so global (chip-spanning) wires dominate timing; this is why designers insert repeaters or thicker upper-level metal to break long

L

into short segments.

EC-6. What happens if the barrier is perfect but has zero thickness (idealized)?

A truly zero-thickness barrier cannot physically block diffusion — the trade is real: you shrink it toward the minimum that still stops copper, never to true zero.

EC-7. What if electroplating fills top-down instead of bottom-up?

Top-down fill pinches the trench mouth shut before the bottom fills, sealing a void inside. Bottom-up "superfill" chemistry exists specifically to avoid this degenerate failure.

The two mental pictures behind every trap

Two figures below carry the ideas that generate almost every misconception on this page. Study each with the questions in mind.

Subtractive vs damascene. The first picture is the fork in the road behind TF-1, TF-3, WHY-1 and WHY-2: on the left, aluminum is deposited everywhere and the unwanted metal is etched away, so the pattern lives in the metal; on the right, the dielectric is carved and copper is inlaid, so the pattern lives in the dielectric. If you can point to which side "the pattern lives in the dielectric" describes, TF-1 can never trap you.

The six-step flow. The second picture is the ordered chain behind SE-2, TF-9, TF-10 and WHY-4: Dig → Line → Seed → Fill → Polish → Cap. Any question that scrambles this order (barrier before dig, cap before fill, seed after fill) is wrong — trace the arrows to confirm the true sequence before answering.

Recall

Recall One-line self-test

Pattern lives in…? → the dielectric
Copper can't be etched because…? → its halides are non-volatile
CMP's real job? → removes overburden to define the wire + planarizes for next layer
"Dual" refers to…? → via + trench filled in one copper step (not shared masks)
Barrier is thinned but never…? → omitted (stops Cu diffusion)
Cap goes on…? → after CMP, on exposed copper top
In $R C \propto ρ ε_{r} ε_{0} L^{2} / (w s)$ , why is $t$ absent? → ==it cancels between $R$ and $C$ ==