Copper damascene process: Worked examples — Hardware deep dive

This page drills the quantitative core of the copper damascene process — the RC delay equations that explain why the industry pays for this whole complicated flow. We build every case: normal numbers, the limiting behaviours, the degenerate ( $t$ cancels!) case, a real word problem, and an exam twist.

We only ever use three formulas from the parent note. Let us restate them so every symbol is earned before use.

The scenario matrix

Here is the full space of cases this topic can throw at you. Every cell is covered by a worked example below.

#	Case class	What is special about it	Covered by
A	Baseline numeric — plain $R$	just plug in, watch unit conversion	Ex 1
B	Ratio / comparison — Cu vs Al	geometry cancels, only $ρ$ survives	Ex 2
C	Capacitance numeric — plain $C$	tiny farads, low-k effect	Ex 3
D	Full $R C$ + limiting law — $L^{2}$ scaling	what happens as $L \to 2 L$ , $L \to 0$	Ex 4
E	Degenerate input — $t$ cancels	change thickness, $R C$ unmoved (R↓, C↑)	Ex 5
F	Zero / extreme input — $s \to 0$ , $w \to 0$	blow-ups, why layout rules exist	Ex 6
G	Real-world word problem — barrier steals area	effective width shrinks, R rises	Ex 7
H	Exam twist — combine low-k + copper, find total speed-up	multiply two independent ratios	Ex 8

Constants used everywhere: $ρ_{C u} = 1.68 \times 1 0^{- 8} Ω \cdot m$ , $ρ_{A l} = 2.65 \times 1 0^{- 8} Ω \cdot m$ , $ε_{0} = 8.854 \times 1 0^{- 12} F/m$ .

The figure above fixes the geometry once for all: a copper line (length $L$ , width $w$ , thickness $t$ ) sitting next to a twin at spacing $s$ . Current runs along the red arrow (that is what $R$ fights); electric field crosses the orange gap sideways (that is what $C$ stores).

Cell A — Baseline resistance

Worked example Ex 1 — plain

$R$ of one copper line $L = 1000 μ m$ , $w = 0.1 μ m$ , $t = 0.2 μ m$ , copper. Find $R$ .

Forecast: guess the order of magnitude first — hundreds of ohms? thousands? Write your guess down.

Convert every length µm → m. $L = 1 0^{- 3} m$ , $w = 1 0^{- 7} m$ , $t = 2 \times 1 0^{- 7} m$ . Why this step? One micron is $1 0^{- 6}$ m. Mixing µm and m is the single most common blunder here (factor $1 0^{6}$ off). Convert before touching the formula.
Cross-section area. $A = w t = 1 0^{- 7} \times 2 \times 1 0^{- 7} = 2 \times 1 0^{- 14} m^{2}$ . Why this step? Current spreads over $A$ ; $R \propto 1/ A$ , so we need it explicitly.
Plug into $R = ρ L / A$ . $R = \frac{1.68 \times 1 0 ^{- 8} \times 1 0 ^{- 3}}{2 \times 1 0 ^{- 14}} = 840 Ω$ . Why this step? This is the definition; steps 1–2 just fed it clean SI numbers.

Verify: units $= \frac{( Ω \cdot m ) ( m )}{m ^{2}} = Ω$ . ✓ And $840 Ω$ for a 1 mm line 100 nm wide is physically sane — thin long wires really are that resistive.

Cell B — Copper vs Aluminum ratio

Worked example Ex 2 — how much faster is copper? (geometry cancels)

Same wire as Ex 1, but built in aluminum instead. Find $R_{A l}$ and the ratio $R_{C u} / R_{A l}$ .

Forecast: copper resistivity is smaller, so is $R_{C u} / R_{A l}$ above or below 1? Guess.

Reuse the same $A$ and $L$ . Nothing geometric changed. Why this step? Aluminum and copper here occupy the same trench shape, so $L / A$ is identical — only $ρ$ differs.
Compute $R_{A l}$ . $R_{A l} = \frac{2.65 \times 1 0 ^{- 8} \times 1 0 ^{- 3}}{2 \times 1 0 ^{- 14}} = 1325 Ω$ . Why this step? Direct plug-in with $ρ_{A l}$ .
Form the ratio. $\frac{R _{C u}}{R _{A l}} = \frac{ρ _{C u}}{ρ _{A l}} = \frac{1.68}{2.65} \approx 0.634$ . Why this step? Because $L / A$ cancels, only the resistivity ratio survives — this is why the parent note's 37% number is geometry-independent.

Verify: $840/1325 = 0.634$ ✓ matches the resistivity ratio exactly. Copper wire is $\approx 37%$ less resistive — the entire commercial reason for damascene.

Cell C — Baseline capacitance

Worked example Ex 3 — line-to-line capacitance, and low-k effect

Two parallel copper wires: $t = 0.2 μ m$ , $L = 1000 μ m$ , spacing $s = 0.1 μ m$ . Compare $C$ in ordinary $SiO_{2}$ ( $ε_{r} = 3.9$ ) versus a low-k dielectric ( $ε_{r} = 2.5$ ).

Forecast: capacitance of something this tiny — femtofarads (fF)? attofarads? Guess the exponent.

Convert. $t = 2 \times 1 0^{- 7}$ , $L = 1 0^{- 3}$ , $s = 1 0^{- 7}$ (all m). Why this step? Same µm→m discipline; farads are unforgiving of scale errors.
Geometry factor. $\frac{t L}{s} = \frac{2 \times 1 0 ^{- 7} \times 1 0 ^{- 3}}{1 0 ^{- 7}} = 2 \times 1 0^{- 3} m$ . Why this step? $C$ is $ε$ times this "shape number"; isolating it lets us swap dielectrics cheaply.
SiO₂ case. $C = 3.9 \times 8.854 \times 1 0^{- 12} \times 2 \times 1 0^{- 3} \approx 6.91 \times 1 0^{- 14} F = 69.1 fF$ .
Low-k case. $C = 2.5 \times 8.854 \times 1 0^{- 12} \times 2 \times 1 0^{- 3} \approx 4.43 \times 1 0^{- 14} F = 44.3 fF$ . Why this step? Only $ε_{r}$ changed, so $C$ scales linearly with it: $69.1 \times (2.5/3.9) = 44.3$ . ✓

Verify: units $= (F/m) (m) = F$ ✓. Ratio $44.3/69.1 = 0.641 = 2.5/3.9$ ✓ — low-k cut capacitance $\approx 36%$ , exactly why low-k rides alongside copper.

Cell D — Full RC and the $L^{2}$ limiting law

Worked example Ex 4 — full

$R C$ , and what happens as the wire gets longer Copper, $ε_{r} = 2.5$ , $L = 1000 μ m$ , $w = 0.1 μ m$ , $s = 0.1 μ m$ . Find $R C$ . Then predict $R C$ if the wire is twice as long, and the limit as $L \to 0$ .

Forecast: if you double $L$ , does $R C$ double or quadruple? Commit before reading.

Use the collapsed formula $R C = ρ ε_{r} ε_{0} \frac{L ^{2}}{w s}$ . Why this step? The parent already cancelled $t$ ; this form shows the pure $L^{2}$ dependence we want to probe.
Plug in (SI): $R C = 1.68 \times 1 0^{- 8} \times 2.5 \times 8.854 \times 1 0^{- 12} \times \frac{( 1 0 ^{- 3} ) ^{2}}{1 0 ^{- 7} \times 1 0 ^{- 7}}$ . $\frac{L ^{2}}{w s} = \frac{1 0 ^{- 6}}{1 0 ^{- 14}} = 1 0^{8}$ . So $R C = 1.68 \times 1 0^{- 8} \times 2.214 \times 1 0^{- 11} \times 1 0^{8} \approx 3.72 \times 1 0^{- 11} s$ . Why this step? Grouping $ε_{r} ε_{0}$ first ( $= 2.214 \times 1 0^{- 11}$ ) keeps the arithmetic tidy. Answer $\approx 37$ ps.
Double the length. $L \to 2 L$ multiplies $L^{2}$ by $4$ : $R C \to 4 \times 3.72 \times 1 0^{- 11} = 1.49 \times 1 0^{- 10} s$ . Why this step? $R C \propto L^{2}$ — the tool that answers "why are long wires killers": delay grows quadratically, not linearly.
Limit $L \to 0$ . $R C \to 0$ . Short local wires are essentially free of $R C$ delay. Why this step? Confirms the degenerate short-wire end of the range — the model behaves sensibly at zero.

Verify: units $= (Ω \cdot m) (F/m) (m^{2} / m^{2}) = Ω \cdot F = s$ ✓. And $R \cdot C$ from Ex 1 & Ex 3 directly: $840 Ω \times 44.3 fF = 3.72 \times 1 0^{- 11} s$ ✓ — the two routes agree.

The curve is a parabola: halving wire length quarters the delay. This is the geometric reason chip designers break long wires with repeaters — but that is a downstream story.

Cell E — Degenerate case: thickness cancels

Worked example Ex 5 — make the wire thicker: does

$R C$ change? Take Ex 4's wire and double the thickness $t$ . What happens to $R$ , to $C$ , and to $R C$ ?

Forecast: thicker copper — surely faster (lower $R$ )? Or does something bite back?

Effect on $R$ . $R = ρ L / (w t)$ , so $t \to 2 t$ gives $R \to R /2 = 420 Ω$ . Why this step? More cross-section = less crowding = less resistance. Intuitive win.
Effect on $C$ . $C = ε_{r} ε_{0} t L / s$ , so $t \to 2 t$ gives $C \to 2 C = 88.6 fF$ . Why this step? Taller sidewalls face the neighbour over a bigger area — the coupling capacitor grows. Hidden cost.
Effect on $R C$ . $R C \to (R /2) (2 C) = R C$ . Unchanged at $3.72 \times 1 0^{- 11} s$ . Why this step? This is the algebraic reason $t$ vanished from the collapsed formula — thickness trades R against C one-for-one. A pure degenerate direction of the model.

Verify: $(420) (88.6 \times 1 0^{- 15}) = 3.72 \times 1 0^{- 11} s$ ✓ identical to Ex 4. So you cannot cheat delay with thickness alone — you must attack $ρ$ (copper) or $ε_{r}$ (low-k) or geometry $L, w, s$ .

Cell F — Zero and extreme inputs

Worked example Ex 6 — push spacing and width toward zero

Using $R C = ρ ε_{r} ε_{0} L^{2} / (w s)$ : what happens as (a) spacing $s \to 0$ , and (b) width $w \to 0$ ?

Forecast: does shrinking the chip make wires faster or slower? Guess for each.

$s \to 0$ : $R C \to \infty$ . As neighbours crowd together, $C \to \infty$ (a parallel-plate capacitor with zero gap has infinite capacitance). Why this step? $C \propto 1/ s$ ; the limit exposes why layout rules impose a minimum spacing — coupling delay (and crosstalk) blow up. Physically before $s = 0$ the wires would short.
$w \to 0$ : $R C \to \infty$ . A vanishing width means vanishing cross-section, so $R \to \infty$ . Why this step? $R \propto 1/ w$ ; the limit is why we cannot make wires arbitrarily thin to save area — resistance explodes.
Sanity midpoint. Halving both $w$ and $s$ (a full shrink): $w s \to w s /4$ , so $R C \to 4 \times R C$ . Why this step? Shows scaling hurts wire delay even though transistors get faster — the historical motivation for copper + low-k in the first place.

Verify: at $w = s = 0.05 μ m$ (both halved), $R C = 4 \times 3.72 \times 1 0^{- 11} = 1.49 \times 1 0^{- 10} s$ ✓ — matches the $\times 4$ prediction and coincidentally equals the doubled-length case of Ex 4 (both multiply the fraction by 4).

Cell G — Real-world word problem: the barrier steals area

Worked example Ex 7 — the

BEOL barrier tax A trench is drawn $w = 0.10 μ m$ wide and $t = 0.20 μ m$ tall. But a $5 nm$ Ta/TaN barrier lines the sides and bottom, and copper only fills the inside. Assume the barrier is far more resistive than copper (treat it as non-conducting for the copper path). By how much does the copper resistance rise versus an ideal barrier-free trench? ( $L = 1000 μ m$ .)

Forecast: 5 nm sounds tiny next to 100 nm. Guess: does $R$ rise by <5%, ~10%, or >15%?

Ideal copper area. $A_{0} = w t = 0.10 \times 0.20 = 0.02 μ m^{2}$ → $2 \times 1 0^{- 14} m^{2}$ (as Ex 1, $R = 840 Ω$ ). Why this step? This is the barrier-free reference.
Barrier eats a rim. The barrier lines both sidewalls and the bottom (open top, since that faces the CMP surface). Copper width shrinks by $2 \times 5 nm = 10 nm$ ; copper height shrinks by $5 nm$ (bottom only). So $w_{C u} = 0.10 - 0.010 = 0.090 μ m$ , $t_{C u} = 0.20 - 0.005 = 0.195 μ m$ . Why this step? The barrier is a physical liner (RIE-etched trench, conformally coated); copper occupies only what is left. This is why engineers push for thinner barriers.
Copper area & new resistance. $A_{C u} = 0.090 \times 0.195 = 0.01755 μ m^{2} = 1.755 \times 1 0^{- 14} m^{2}$ . $R_{C u} = \frac{1.68 \times 1 0 ^{- 8} \times 1 0 ^{- 3}}{1.755 \times 1 0 ^{- 14}} \approx 957 Ω$ . Why this step? Same $R = ρ L / A$ ; only the usable area changed.
Percentage rise. $\frac{957 - 840}{840} \approx 0.139 = 13.9%$ . Why this step? Converts the abstract area loss into the number a designer feels.

Verify: $A_{0} / A_{C u} = 0.02/0.01755 = 1.139$ ✓ matches the 13.9% rise. Lesson: a "tiny" 5 nm barrier costs ~14% resistance on a 100 nm wire — barrier thinning is a real research battlefront, and never omitting it protects against electromigration and Cu diffusion.

Cell H — Exam twist: stack two independent wins

Worked example Ex 8 — total speed-up from copper AND low-k together

An old technology uses aluminum in $SiO_{2}$ ( $ε_{r} = 3.9$ ). A new one uses copper in low-k ( $ε_{r} = 2.5$ ), same geometry. By what factor does $R C$ improve, and what is the percentage delay reduction?

Forecast: two improvements of ~37% and ~36% — do they add (~73%) or multiply? Guess.

Write $R C$ as a product of independent factors. $R C = metal ρ \cdot dielectric ε_{r} \cdot geometry, unchanged ε_{0} L^{2} / (w s)$ . Why this step? Because geometry is identical, only $ρ$ and $ε_{r}$ change — and they multiply, so the improvements compound, not add.
Resistivity ratio. $ρ_{C u} / ρ_{A l} = 1.68/2.65 = 0.634$ (from Ex 2).
Permittivity ratio. $ε_{r, new} / ε_{r, old} = 2.5/3.9 = 0.641$ (from Ex 3).
Combined factor. $0.634 \times 0.641 = 0.406$ . Why this step? Multiplying the two ratios gives the new-to-old $R C$ ratio.
Percentage reduction. $1 - 0.406 = 0.594 = 59.4%$ faster. Why this step? Converts the surviving fraction into the headline delay cut.

Verify: $0.634 \times 0.641 = 0.4064$ ✓. Note $59.4% \neq = 37% + 36% = 73%$ — they compound multiplicatively, giving a smaller combined win than a naive sum. That is the exam trap: do not add percentage improvements; multiply the surviving fractions.

Recall

Recall Cover the answers

In the Cu-vs-Al $R$ ratio, why does geometry vanish? ::: same trench, so $L / A$ is identical; only $ρ$ survives
If you double a wire's length, $R C$ changes by what factor? ::: $\times 4$ (it scales as $L^{2}$ )
Double the thickness $t$ : what happens to $R C$ ? ::: nothing — $R$ halves, $C$ doubles, product unchanged
As spacing $s \to 0$ , what blows up and why? ::: $C \to \infty$ (parallel-plate with zero gap)
Why does a 5 nm barrier cost ~14% resistance on a 100 nm wire? ::: it lines the trench and shrinks the copper cross-section area
Combine a 37% and 36% improvement — total? ::: multiply fractions $0.634 \times 0.641 = 0.406$ → ~59% faster, NOT 73%