Level 4 — ApplicationSemiconductor Fabrication

Semiconductor Fabrication

⏱ 60 minutes60 marksprintable — key stays hidden on paper

Level 4 — Application (novel problems, no hints) Time limit: 60 minutes Total marks: 60

Use $...$ for inline math and $...$ for display. Show all working. Physical constants: Avogadro $N_A = 6.022\times10^{23}\ \text{mol}^{-1}$ ; silicon density $2.33\ \text{g/cm}^3$ ; silicon molar mass $28.09\ \text{g/mol}$ .

Question 1 — Lithography resolution and multi-patterning (14 marks)

A fab runs an ArF immersion DUV scanner ( $\lambda = 193\ \text{nm}$ ) with a numerical aperture $NA = 1.35$ .

(a) Using the Rayleigh criterion $CD = k_1 \lambda / NA$ with a single-exposure process factor $k_1 = 0.30$ , compute the minimum resolvable half-pitch. (3)

(b) The target design requires a 20 nm half-pitch metal layer. Determine how many times you must divide the pitch (i.e. the multi-patterning factor $N$ , where achievable half-pitch $= \text{single-exposure HP}/N$ ) to reach the target, rounding $N$ up to the nearest integer power-of-two-compatible value used in LELE/SADP schemes. State whether SADP (self-aligned double patterning) alone is sufficient. (4)

(c) An EUV scanner with $\lambda = 13.5\ \text{nm}$ and $NA = 0.33$ is proposed as an alternative. Compute its single-exposure half-pitch at the same $k_1 = 0.30$ , and state one physical reason EUV needs reflective (not transmissive) optics. (4)

(d) Give one manufacturing disadvantage of reaching 20 nm HP by multi-patterning versus by EUV single exposure. (3)

Question 2 — Thermal oxidation budget (12 marks)

A wafer is oxidized to grow a gate-quality $\text{SiO}_2$ layer. In the linear (thin-oxide) regime the oxide thickness grows as $x_{ox} = (B/A)\,t$ , where the linear rate constant $B/A = 0.05\ \mu\text{m/hr}$ at the process temperature.

(a) Compute the time required to grow a 4 nm oxide in the linear regime. (3)

(b) Growing $\text{SiO}_2$ consumes underlying silicon. Given that $0.44$ nm of Si is consumed per 1.0 nm of oxide grown, compute the silicon thickness consumed for the 4 nm oxide, and the net surface height change relative to the original Si surface (state whether the oxide surface sits above or below the original surface). (5)

(c) Explain, in terms of the Deal–Grove model, why doubling the target oxide thickness in the parabolic (thick-oxide) regime requires roughly four times the oxidation time. (4)

Question 3 — Wafer economics, yield and binning (16 marks)

A 300 mm wafer is patterned with square dies of edge 8 mm.

(a) Estimate the maximum number of whole dies per wafer using $N \approx \dfrac{\pi (D/2)^2}{S} - \dfrac{\pi D}{\sqrt{2S}}$ , where $D$ is wafer diameter and $S$ is die area. Show both terms. (4)

(b) Using the Poisson yield model $Y = e^{-D_0 A}$ with defect density $D_0 = 0.15\ \text{defects/cm}^2$ and die area $A$ (in cm²), compute the yield and the expected number of good dies. (5)

(c) The good dies are binned by max stable clock: 30% at 3.5 GHz, 45% at 3.0 GHz, 25% at 2.5 GHz. Selling prices are $210, $150, $95 respectively. Compute expected revenue per wafer from good dies. (4)

(d) Management wants to raise yield to 0.90. Compute the required defect density $D_0$ and comment on whether this is more realistically achieved via process cleanliness or die-size reduction. (3)

Question 4 — Transistor scaling: FinFET → GAA (10 marks)

(a) A FinFET has a rectangular fin of height $H_{fin} = 42\ \text{nm}$ and width $W_{fin} = 8\ \text{nm}$ , gated on three sides. Compute the effective electrostatic channel width $W_{eff}$ per fin. (3)

(b) A gate-all-around nanosheet device replaces this fin with a stack of 3 nanosheets, each $30\ \text{nm}$ wide and $5\ \text{nm}$ thick, gated on all four sides. Compute $W_{eff}$ for the stack. (4)

(c) State one electrostatic advantage of the GAA geometry over FinFET that is not captured purely by the $W_{eff}$ number. (3)

Question 5 — Copper damascene & deposition sequence (8 marks)

(a) List, in correct process order, the main steps of a single (Cu) damascene interconnect module, from dielectric deposition to a planar Cu-filled trench. (4)

(b) Explain why electroplated Cu requires both a barrier layer and a seed layer, naming a typical technique used to deposit each. (4)

Answer keyMark scheme & solutions

Question 1 (14)

(a) $CD = k_1\lambda/NA = 0.30 \times 193 / 1.35 = 57.9/1.35 = 42.9\ \text{nm}$ . So single-exposure half-pitch $\approx 42.9\ \text{nm}$ . (3) — (1 formula, 1 substitution, 1 answer)

(b) Need HP = 20 nm. $N = 42.9/20 = 2.14$ . Round up to a multi-patterning-compatible value → $N = 4$ (LELE gives ×2, LELELE/SADP schemes go ×2, ×4). A single SADP gives factor 2 → HP $= 42.9/2 = 21.4\ \text{nm}$ , which is just above 20 nm target, so SADP alone is marginal/insufficient; SAQP (×4) or LE³ is safely required. (4) — (1 for $N$ calc, 1 rounding, 1 SADP HP=21.4 nm, 1 conclusion)

(c) EUV: $CD = 0.30 \times 13.5 / 0.33 = 4.05/0.33 = 12.3\ \text{nm}$ single exposure — easily resolves 20 nm HP in one pass. EUV needs reflective optics because 13.5 nm light is strongly absorbed by all known lens materials (no transmissive glass), so mirrors (Mo/Si multilayer Bragg reflectors) and vacuum are used. (4) — (1 formula, 1 = 12.3 nm, 1 single-exposure OK, 1 absorption reason)

(d) Any one: multi-patterning multiplies cost/time (2–4× the exposures + intermediate etch/deposition), increases overlay/edge-placement error, and lowers throughput/yield versus one EUV exposure. (3)

Question 2 (12)

(a) $t = x_{ox}/(B/A) = 0.004\ \mu\text{m} / 0.05\ \mu\text{m/hr} = 0.08\ \text{hr} = 4.8\ \text{min}$ . (3)

(b) Si consumed $= 0.44 \times 4 = 1.76\ \text{nm}$ . Oxide grows 4 nm total but 1.76 nm of it is below the original Si surface; the oxide top rises $4 - 1.76 = 2.24\ \text{nm}$ above the original Si surface. (5) — (2 consumed, 2 net rise, 1 direction)

(c) In parabolic regime $x_{ox}^2 \approx B t$ (diffusion of oxidant through existing oxide is rate-limiting). Since $x_{ox}\propto\sqrt{t}$ , doubling $x_{ox}$ needs $t$ increased by $2^2 = 4$ . Physically the growing oxide layer lengthens the diffusion path for oxidant to reach the Si/SiO₂ interface, slowing growth. (4)

Question 3 (16)

(a) $D = 300\ \text{mm}$ , $S = 64\ \text{mm}^2$ . Term1 $= \pi(150)^2/64 = \pi\cdot22500/64 = 1104.5$ . Term2 $= \pi\cdot300/\sqrt{128} = 942.48/11.314 = 83.3$ . $N \approx 1104.5 - 83.3 = 1021\ \text{dies}$ (≈1021). (4)

(b) $A = 0.64\ \text{cm}^2$ ; $Y = e^{-0.15\times0.64} = e^{-0.096} = 0.9085$ . Good dies $= 1021 \times 0.9085 = 927.6 \approx 928$ . (5)

(c) Weighted price per good die $= 0.30(210)+0.45(150)+0.25(95) = 63+67.5+23.75 = 154.25$ . Revenue $= 928 \times 154.25 = \$ 143{,}144 $(≈\$ 143k). (4)

(d) $0.90 = e^{-D_0(0.64)} \Rightarrow D_0 = -\ln(0.90)/0.64 = 0.10536/0.64 = 0.1646\ \text{defects/cm}^2$ . This is above the current 0.15, so current yield already ~0.91 > 0.90 — target is already met; alternatively reducing die area also raises yield. Comment: cleanliness (lower $D_0$ ) and smaller dies both help; here yield already exceeds 0.90. (3)

Question 4 (10)

(a) Tri-gate: $W_{eff} = 2H_{fin} + W_{fin} = 2(42)+8 = 92\ \text{nm}$ . (3)

(b) Per sheet (all-around): perimeter $= 2(W+t) = 2(30+5) = 70\ \text{nm}$ . Stack of 3: $W_{eff}=3\times70 = 210\ \text{nm}$ . (4)

(c) GAA wraps the gate fully around the channel, giving superior electrostatic control (better subthreshold slope, reduced short-channel effects/DIBL, lower leakage) and allowing continued gate-length scaling — not captured by width alone. (3)

Question 5 (8)

(a) Order: (1) deposit dielectric (ILD/low-k, CVD) → (2) pattern & etch trench (litho + dry etch) → (3) deposit barrier + Cu seed (PVD/ALD) → (4) electroplate Cu overfill → (5) CMP to planarize/remove overburden leaving Cu in trench. (4)

(b) Barrier (e.g. TaN/Ta by PVD or ALD) prevents Cu from diffusing into and poisoning the surrounding dielectric/Si; seed (thin Cu, by PVD/sputtering) provides a conductive, continuous surface for uniform electroplating to nucleate on. (4)

[
  {"claim":"DUV single-exposure half-pitch = 42.9 nm","code":"cd=0.30*193/1.35; result = abs(cd-42.888)<0.05"},
  {"claim":"EUV single-exposure half-pitch = 12.3 nm","code":"cd=0.30*13.5/0.33; result = abs(cd-12.27)<0.05"},
  {"claim":"Oxide net rise above original Si = 2.24 nm","code":"rise=4-0.44*4; result = abs(rise-2.24)<0.001"},
  {"claim":"Poisson yield = 0.9085 for D0=0.15, A=0.64","code":"Y=exp(-Rational(15,100)*Rational(64,100)); result = abs(float(Y)-0.90848)<0.001"},
  {"claim":"Dies per wafer approx 1021","code":"N=pi*150**2/64 - pi*300/sqrt(128); result = abs(float(N)-1021)<1.5"},
  {"claim":"Weighted die price = 154.25","code":"p=0.30*210+0.45*150+0.25*95; result = abs(p-154.25)<1e-9"},
  {"claim":"GAA stack Weff = 210 nm","code":"w=3*2*(30+5); result = w==210"}
]