Copper damascene process — Hinglish notes

4.3.17 · Hardware › Semiconductor Fabrication

YE PROCESS EXIST KYUN KARTI HAI?

Copper kyun, aluminum kyun nahi?

Copper resistivity $ρ_{C u} \approx 1.68 μ Ω \cdot cm$ vs aluminum $ρ_{A l} \approx 2.65 μ Ω \cdot cm$ → ~40% kam → less RC delay, faster chips.
Copper electromigration ko bahut better resist karta hai (higher activation energy) → high current density par zyada reliable.

Copper ko aluminum ki tarah etch kyun nahi karte?

Aluminum ko reactive ion etching (RIE) se pattern kiya jaata hai: ek metal blanket deposit karo, mask karo, aur unwanted metal ko etch kar do kyunki Al volatile chlorides banaata hai ( $AlCl_{3}$ boil off ho jaata hai).
Copper halides ( $CuCl$ , $CuF_{2}$ ) reasonable temperatures par NOT volatile hote hain → inhe gas ke roop mein etch off nahi kar sakte. Isliye subtractive etching fail ho jaati hai.
Fix (damascene ka poora point): problem ko inside-out karo — dielectric (SiO₂ / low-k) ko etch karo, jo aasaani se etch hoti hai, phir copper inlay karo.

DO FLAVOURS KYA HAIN?

Dual damascene modern back-end-of-line (BEOL) ke liye industry standard hai.

KAISE: dual damascene flow, step by step

Dielectric deposit karo (SiO₂ ya low-k) lower metal ke upar wafer par. Kyun? Ye wahi material hai jisme hum wire shape carve karenge.
Via + trench etch karo dielectric mein photolithography + RIE use karke (do lithography masks: ek via ke liye, ek trench ke liye). RIE yahan kyun kaam karta hai: SiO₂ volatile fluorides ( $SiF_{4}$ ) mein etch hoti hai — aasaan, copper ki tarah nahi.
Barrier layer deposit karo (Ta / TaN, ~kuch nm) trench ko conformally line karte hue. Kyun? Copper silicon aur SiO₂ mein fast diffuse karta hai, transistors ko poison karta hai (deep-level traps). Barrier Cu diffusion block karta hai aur adhesion improve karta hai.
Copper seed layer deposit karo (thin PVD Cu). Kyun? Electroplating ko current carry karne ke liye ek conductive starting surface chahiye.
Electroplate (ECD) copper karo trench + via ko overfill karne ke liye (bottom-up superfill). Overfill kyun? Guarantee karta hai ki trench ke andar koi voids nahi honge; excess agle step mein remove hoga.
CMP (Chemical Mechanical Polish) se copper overburden aur barrier ko dielectric surface tak remove karo — copper sirf trenches ke andar reh jaata hai. Kyun? Ye surface ko planarize karta hai taaki next layer flat build ho sake (lithography depth-of-focus ke liye essential).
Capping layer deposit karo (e.g. SiN, SiCN) upar. Kyun? CMP ke baad copper ki top surface exposed hoti hai; cap Cu oxidation/upward diffusion ko rokta hai aur top interface ke saath electromigration block karta hai.
Next metal level ke liye repeat karo.

PHYSICS JO MOTIVATE KARTI HAI — RC delay derive karna

Recall

Recall Active recall — answers cover karo

Copper ko aluminum ki tarah subtractively etch kyun nahi kiya ja sakta? → iske halides non-volatile hain
Damascene mein wire pattern kahan define hota hai? → dielectric mein, metal mein nahi
Copper aur dielectric ke beech mein kya deposit hota hai, aur kyun? → Ta/TaN barrier Cu diffusion rokne ke liye
Dual damascene mein "dual" ka matlab kya hai? → via + trench ek copper step mein fill hote hain
Copper overburden kya remove karta hai? → CMP
Copper aluminum se better kyun? → lower resistivity (~37% less RC) + better electromigration

Recall Feynman: 12-year-old ko explain karo

Imagine karo tumhe knife par gold ki vines chahiye. Tum gold ko surface par melt karke galat bits cut nahi kar sakte — gold smear ho jaata hai. Isliye instead steel mein vines ki shape ke grooves carve karo, grooves mein molten gold daalo, aur phir top sand karo jab tak gold sirf grooves ke andar dikhe. Computer chips exactly yahi karte hain: ve tiny wire-shaped ditches glass mein carve karte hain, unhe copper se fill karte hain, aur top ko smooth sand karte hain. Ve ditches ko ek thin "raincoat" (barrier) se bhi line karte hain taaki copper glass mein leak na ho aur cheezein kharab na kare.

Flashcards

Copper ko damascene se kyun pattern kiya jaata hai instead of subtractive etch se?

Copper halide etch byproducts non-volatile hote hain, isliye copper ko cleanly dry-etch nahi kiya ja sakta; damascene copper ko pre-etched dielectric trenches mein inlay karta hai instead.

Damascene mein wire pattern kaunsa material carry karta hai?

Dielectric (insulator) — usme etched trenches wires define karti hain.

Dual damascene kya hai?

Ek process jisme via aur uske upar ka trench dono dielectric mein etch kiye jaate hain aur ek single metal-deposition step mein copper se fill kiye jaate hain.

Ta/TaN barrier layer ka purpose?

Copper diffusion ko dielectric/silicon mein block karna aur adhesion improve karna.

Electroplating se pehle copper seed layer kyun?

Electroplating ko bottom-up copper fill ke liye current flow start karne ke liye ek conductive surface chahiye.

Damascene mein CMP kya karta hai?

Copper overburden aur barrier ko dielectric tak remove karta hai, copper sirf trenches mein rakhta hai, aur next layer ke liye surface planarize karta hai.

Interconnects ke liye copper aluminum se better kyun?

Lower resistivity (1.68 vs 2.65 µΩ·cm → ~37% lower RC delay) aur better electromigration resistance.

Interconnect resistance ka formula?

R = ρL/(w·t).

RC delay wire length ke saath kaise scale karta hai?

L^{2}

ke saath — long global wires delay dominate karti hain.

CMP ke baad copper ke upar capping layer kyun?

Cu oxidation/upward diffusion rokne ke liye aur top interface ke saath electromigration suppress karne ke liye.

Connections

Chemical Mechanical Polishing (CMP)
Reactive Ion Etching
Low-k dielectrics
Electromigration
Back-End-Of-Line (BEOL)
Photolithography
RC delay in interconnects
Aluminum metallization (subtractive)