WHY separate FEOL and BEOL? Transistors need high-temperature steps (implant anneal ~1000 °C). Metals like aluminum/copper melt or diffuse at those temperatures, so wiring must come after the hot device steps are finished.
Resistance of a wire:
R=ρAL=ρWHL
where ρ = resistivity, L = length, W=width, H=height (cross-section A=WH).
WHY copper wins:ρCu≈1.7μΩ⋅cm vs ρAl≈2.7μΩ⋅cm. Lower ρ ⇒ lower R ⇒ faster, cooler chips. Copper also resists electromigration (atoms drifting under high current, which breaks aluminum wires) far better.
But — copper cannot be etched easily by plasma (its halides aren't volatile). So a different trick is used: the damascene process.
Instead of "deposit metal → etch it into wires," damascene does the reverse: "carve trenches in the dielectric → fill with copper → polish flat."
Deposit dielectric (ILD) over the surface.
Etch trenches/vias into the dielectric where wires should go (patterned by lithography).
Deposit a barrier layer (e.g. Ta/TaN) — WHY? Copper diffuses into silicon/dielectric and poisons transistors; the barrier is a wall stopping it.
Deposit a copper seed layer, then electroplate copper to overfill the trenches.
CMP (Chemical-Mechanical Planarization): grind/polish away the copper that sits above the trenches, leaving copper only inside the trenches — perfectly flat.
Lowers inter-wire capacitance C=kε0A/d, reducing RC delay and dynamic power.
What is a via vs a contact?
Via connects two metal layers; contact connects Metal-1 down to the transistor silicon.
What dominates delay in advanced nodes, gate delay or RC interconnect delay?
Interconnect RC delay increasingly dominates, driving Cu + low-k adoption.
Recall Feynman: explain to a 12-year-old
Imagine you built a city full of tiny light-switches (transistors) but forgot the wires. Metallization is putting in all the wires and connectors. Old wires were made of aluminum, but engineers found copper wires let electricity flow faster and don't wear out as quickly. Copper is hard to cut into thin wires, so instead they carve tiny grooves in a glass-like layer, pour copper in, and polish the top smooth — like filling cracks in a floor with metal and sanding it flat. They stack many floors of these wires so millions of connections never bump into each other.
Dekho, jab chip ke andar saare transistors ban jaate hain (FEOL), tab woh sirf alag-alag switch hote hain — beech mein koi wiring nahi. Metallization ka kaam hai in switches ko metal ke wires se jodna. Ye phase BEOL kehlata hai kyunki high-temperature transistor steps ke baad hi hota hai, warna metal pighal ya diffuse ho jaayega.
Pehle aluminium wires use hote the, par jaise-jaise wires patle hote gaye, unki resistance badh gayi aur RC delay chip ki speed ko limit karne laga. Isliye copper aaya — kyunki copper ki resistivity kam hai (formula: R=ρL/WH, kam ρ matlab kam R), aur copper electromigration bhi jhelta hai better. Problem ye hai ki copper ko plasma se etch nahi kar sakte, isliye ek ulta trick use karte hain jise damascene kehte hain: dielectric mein groove (trench) kaato, uske andar copper bharo, phir CMP se upar ka extra copper ghis kar flat kar do. Copper diffuse na ho isliye pehle ek barrier layer (Ta/TaN) lagate hain.
Speed aur power dono ke liye do cheezein minimize karni hoti hain: resistance R (isliye copper) aur capacitance C (isliye low-k dielectric, kyunki C=kε0A/d). Aur ek hi layer se kaam nahi chalta — millions of connections ke liye kai layers (Metal-1, Metal-2, …) stack karte hain, jaise multi-level highway. Neeche patle dense wires local routing ke liye, upar mote wires power aur global signals ke liye. Yaad rakho: "Dig, Block, Fill, Flatten" — yahi damascene ki recipe hai.
