4.3.16 · D5Semiconductor Fabrication
Question bank — Metallization and interconnect layers
True or false — justify
The chip's transistors are built first, then the wiring — so anything that reverses that order, or treats copper like aluminum, is where these traps hide.
Metallization happens before the transistors are formed.
False — it is the FEOL transistors that come first; wiring is BEOL, done after the ~1000 °C anneals that would melt or diffuse the metal.
Copper wires are patterned by depositing a copper sheet and plasma-etching the gaps away.
False — copper's etch by-products (halides) are not volatile, so subtractive etch fails; copper wiring uses the additive damascene (inlay) method instead.
Lowering the dielectric constant reduces the wire's resistance.
False — sits in the capacitance , not in resistance ; low-k lowers , which cuts the delay, but is untouched.
Aluminum has lower resistivity than copper.
False — copper is the lower one ( vs ), which is exactly why copper replaced aluminum.
A "contact" and a "via" are the same thing.
False — a contact joins Metal-1 down to the transistor silicon (source/drain/gate); a via joins one metal layer to the next metal layer above or below.
CMP is optional in the damascene flow.
False — damascene deliberately overfills the trenches, so CMP is essential to grind the excess copper off and leave metal only inside the trenches, flat and isolated.
Stacking more metal layers only adds cost and never helps performance.
False — extra layers let millions of nets route without crossing, and thick upper layers carry low-resistance power/global signals; it is a multi-level highway, not just overhead.
The barrier layer's main job is to make copper stick better to the dielectric.
False — adhesion is a side benefit; its primary role is a diffusion wall stopping copper from poisoning silicon/dielectric with deep-level traps.
Spot the error
Read each statement, find the wrong word or clause, and state the correct version.
"Copper resists electromigration worse than aluminum, so it needs wider wires."
Error: "worse" — copper resists electromigration better than aluminum, which is a second reason (besides low ) it replaced it.
"In dual damascene, the via and the trench are each filled and polished separately."
Error: "separately" — the whole point of dual damascene is that via + trench are filled in one copper deposition and cleared in one CMP step, saving steps and improving alignment.
"We use low-k dielectric because it conducts current between wires more slowly."
Error: a dielectric is an insulator — it doesn't conduct; low-k reduces the capacitance between neighbouring wires, cutting delay.
"Resistance scales as , so a longer wire has lower resistance."
Error: the formula is — resistance rises with length and falls with cross-section, so longer means higher .
"Barrier metals like Ta/TaN are deposited to lower the wire's overall resistivity."
Error: barriers are relatively resistive; they exist to block copper diffusion, and in fact eat into the copper cross-section, slightly raising effective resistance.
"After CMP the copper sits proud above the dielectric, ready for the next layer."
Error: CMP leaves the copper flush (flat) with the dielectric — a planar surface is required so the next layer's lithography stays in focus.
Why questions
Each answer should name the mechanism, not just restate the fact.
Why must metals be deposited only after the high-temperature transistor steps?
Because implant-anneal temperatures (~1000 °C) would melt aluminum or drive rapid copper diffusion; the metal must survive, so it follows the hot FEOL steps.
Why did shrinking wire dimensions make interconnect delay dominate over gate delay?
As and shrink, climbs sharply while gate delay keeps falling, so the wire's RC delay becomes the bottleneck — pushing Cu + low-k.
Why does a copper seed layer get deposited before electroplating?
Electroplating needs a conductive, continuous starting surface to grow copper on; the thin PVD seed provides that uniform electrical base inside the trench.
Why is copper diffusion into silicon so dangerous?
Copper atoms create deep-level traps in the silicon band gap that kill carrier lifetime and ruin transistor behaviour — hence the mandatory barrier layer.
Why does damascene "carve then fill" instead of "deposit then etch"?
Because copper can't be cleanly plasma-etched (non-volatile by-products), so the pattern is etched into the dielectric by lithography and copper is inlaid to take that shape.
Why do upper metal layers tend to be thicker and wider than lower ones?
They carry global signals and power where low resistance matters more than density, so wider/taller cross-sections cut ; lower layers stay thin for dense local routing.
Edge cases
The formulas hide interesting behaviour at their limits — probe them.
If a wire's width is halved with everything else fixed, what happens to its resistance?
It doubles — , so halving halves the cross-section and doubles resistance, the core reason thin nodes suffer.
What happens to inter-wire capacitance as two wires are pushed closer (smaller )?
rises (it scales as ), worsening RC delay and crosstalk — which is why tighter pitches demand low-k dielectrics to compensate.
In the limit (vacuum/air gap), what does the capacitance approach?
The smallest possible for that geometry, , since is vacuum — this is why "air-gap" dielectrics are the ultimate low-k target.
If the barrier layer were made zero-thickness, what two things would go wrong?
Copper would diffuse into the dielectric/silicon (device failure) and adhesion would degrade — so a finite minimum barrier is unavoidable even though it steals conductor area.
For a wire of zero length (), what does predict, and is it physical?
It predicts ; the resistive drop along the line vanishes, though real contacts/vias still add resistance the ideal formula ignores.
As copper wires get so narrow that approaches the electron mean free path, does resistivity stay constant?
No — surface and grain-boundary scattering make effective rise above bulk copper, eroding copper's advantage at the smallest nodes.
Recall One-line self-test
Cover everything: name the single reason copper can't be plasma-etched, and the single primary reason a barrier is needed. Copper etch by-products aren't volatile; the barrier blocks copper diffusion into silicon/dielectric. ::: Both correct means you've internalised the two most-tested traps.