Metallization and interconnect layers: Exercises — Hardware deep dive

Before we start, here are the only tools you need, defined from zero so no symbol appears un-earned.

Signal delay of a wire is set by the product $R C$ — the time to charge it up. That single product is the villain the whole chapter fights.

Level 1 — Recognition

L1.1 — Metallization belongs to which fabrication phase, FEOL or BEOL, and why can't it be swapped with the other?

L1.2 — Name the metal that replaced aluminium for interconnect, and state its resistivity vs aluminium's (from the parent note).

L1.3 — In the damascene recipe "Dig, Block, Fill, Flatten", which physical process is "Flatten", and what does it physically remove?

Recall Solution — L1

L1.1 — Metallization is BEOL (Back-End-Of-Line). Transistors are built first in FEOL and their doping needs anneals near $1000^{\circ} C$ . Aluminium/copper would melt or diffuse at that heat, so the wiring must be laid after the hot device steps. See Front-End-Of-Line (FEOL) transistor formation.

L1.2 — Copper, $ρ_{Cu} \approx 1.7 μ Ω \cdot cm$ versus $ρ_{Al} \approx 2.7 μ Ω \cdot cm$ . Lower $ρ$ means lower $R$ for the same wire shape.

L1.3 — "Flatten" is CMP (Chemical-Mechanical Planarization). It grinds/polishes away the copper overfill sitting above the trenches, leaving copper only inside the trenches and a perfectly flat surface for the next layer. See Chemical-Mechanical Planarization (CMP).

Level 2 — Application

L2.1 — A copper line has $L = 200 μ m$ , $W = 40 nm$ , $H = 80 nm$ , $ρ = 1.7 \times 1 0^{- 8} Ω \cdot m$ . Find its resistance $R$ .

L2.2 — Two parallel wires face each other over area $A = 2 \times 1 0^{- 14} m^{2}$ separated by $d = 60 nm$ of dielectric with $k = 2.7$ . Find the capacitance $C$ . ( $ε_{0} = 8.854 \times 1 0^{- 12} F/m$ .)

L2.3 — Keep the L2.1 geometry but swap copper for aluminium ( $ρ = 2.7 \times 1 0^{- 8} Ω \cdot m$ ). By what factor does $R$ rise?

Recall Solution — L2

L2.1 — Step 1 (WHAT): build the cross-section $A = W H$ , because $R$ needs area, not width alone. $A = (40 \times 1 0^{- 9}) (80 \times 1 0^{- 9}) = 3.2 \times 1 0^{- 15} m^{2}$ Step 2 (WHY): now every symbol in $R = ρ L / A$ is a number, so substitute. $R = \frac{( 1.7 \times 1 0 ^{- 8} ) ( 200 \times 1 0 ^{- 6} )}{3.2 \times 1 0 ^{- 15}} = \frac{3.4 \times 1 0 ^{- 12}}{3.2 \times 1 0 ^{- 15}} = 1062.5 Ω$ So $R \approx 1.06 k Ω$ — one skinny wire already over a kilohm; that is why RC delay and interconnect scaling hurts at small nodes.

L2.2 — Plug straight into $C = k ε_{0} A / d$ : $C = \frac{( 2.7 ) ( 8.854 \times 1 0 ^{- 12} ) ( 2 \times 1 0 ^{- 14} )}{60 \times 1 0 ^{- 9}} = 7.97 \times 1 0^{- 18} F \approx 7.97 aF$ (aF = attofarad = $1 0^{- 18}$ F). Tiny per wire, but multiplied over millions of wires it dominates dynamic power.

L2.3 — Only $ρ$ changed, and $R \propto ρ$ , so the ratio is the resistivity ratio: $\frac{R _{Al}}{R _{Cu}} = \frac{2.7 \times 1 0 ^{- 8}}{1.7 \times 1 0 ^{- 8}} = 1.588$ Aluminium would be ~1.59× the resistance — about 59% worse. No new full calc needed.

Level 3 — Analysis

L3.1 — A design team switches the inter-metal dielectric from $SiO_{2}$ ( $k = 3.9$ ) to a low-k material ( $k = 2.4$ ), geometry unchanged. What fraction of the original capacitance remains, and by what percent does dynamic power $P = \frac{1}{2} C V^{2} f$ drop (voltage and frequency fixed)?

L3.2 — For a wire, $R C$ delay scales as $t \propto ρ k \frac{L ^{2}}{W H d}$ with the parent's plate model (take $A_{cap} = L H$ and cross-section $W H$ ). If a node shrink halves $W$ , $H$ , and $d$ but keeps $L$ the same, what happens to $t$ ? Explain physically.

L3.3 — Look at the layer stack figure. Explain why the lowest metal layers are made thin and dense while the upper layers are made thick and wide.

Figure — Metallization and interconnect layers

Recall Solution — L3

L3.1 — With geometry fixed, $C \propto k$ , so $\frac{C _{low-k}}{C _{SiO_{2}}} = \frac{2.4}{3.9} = 0.6154$ About 61.5% of the capacitance remains, i.e. a 38.5% drop. Since $P = \frac{1}{2} C V^{2} f$ is linear in $C$ (with $V, f$ fixed), power also drops 38.5%. This is exactly why Low-k dielectric materials are worth their integration pain.

L3.2 — Substitute the scale factors. $L$ unchanged. $W \to W /2$ , $H \to H /2$ , $d \to d /2$ : $t \propto \frac{L ^{2}}{( W /2 ) ( H /2 ) ( d /2 )} = \frac{L ^{2}}{W H d} \cdot 8$ Delay goes 8× worse. Physically: thinner $W, H$ shrink the cross-section, so $R$ climbs ( $R \propto 1/ W H$ ); a smaller gap $d$ raises $C$ ( $C \propto 1/ d$ ). Both fight you at once. This is the core message of RC delay and interconnect scaling: shrinking transistors is easy, but shrinking wires makes interconnect delay explode — the reason copper + low-k + more layers were all needed.

L3.3 — In the figure the bottom layers (magenta, thin) carry dense local routing — millions of short connections between nearby transistors, so they must be narrow to pack tightly. The top layers (orange, thick, wide) carry global signals and power/ground: these run long distances, so their resistance must stay low, and $R \propto L / (W H)$ — a wide, tall cross-section keeps $R$ down over long $L$ . Fat upper wires also carry big currents without electromigration failure.

Level 4 — Synthesis

L4.1 — A chip uses two wiring options for the same $L = 150 μ m$ , $W = 50 nm$ , $H = 90 nm$ line and the same capacitance geometry ( $A_{cap} = 6 \times 1 0^{- 15} m^{2}$ , $d = 50 nm$ ):

Option A: aluminium ( $ρ = 2.7 \times 1 0^{- 8}$ ) + $SiO_{2}$ ( $k = 3.9$ )

Option B: copper ( $ρ = 1.7 \times 1 0^{- 8}$ ) + low-k ( $k = 2.6$ )

Compute $R$ , $C$ , and the $R C$ delay for each, then the improvement factor $t_{A} / t_{B}$ .

L4.2 — Explain, step by step, why Option B's improvement in $t_{A} / t_{B}$ equals the product of the resistivity ratio and the $k$ ratio, and confirm it numerically.

Recall Solution — L4

L4.1 — Cross-section $A = W H = (50 \times 1 0^{- 9}) (90 \times 1 0^{- 9}) = 4.5 \times 1 0^{- 15} m^{2}$ .

Resistances ( $R = ρ L / A$ , with $L = 150 \times 1 0^{- 6}$ ): $R_{A} = \frac{( 2.7 \times 1 0 ^{- 8} ) ( 150 \times 1 0 ^{- 6} )}{4.5 \times 1 0 ^{- 15}} = 900 Ω$ $R_{B} = \frac{( 1.7 \times 1 0 ^{- 8} ) ( 150 \times 1 0 ^{- 6} )}{4.5 \times 1 0 ^{- 15}} = 566.67 Ω$

Capacitances ( $C = k ε_{0} A_{cap} / d$ , $A_{cap} = 6 \times 1 0^{- 15}$ , $d = 50 \times 1 0^{- 9}$ ): $C_{A} = \frac{( 3.9 ) ( 8.854 \times 1 0 ^{- 12} ) ( 6 \times 1 0 ^{- 15} )}{50 \times 1 0 ^{- 9}} = 4.144 \times 1 0^{- 18} F$ $C_{B} = \frac{( 2.6 ) ( 8.854 \times 1 0 ^{- 12} ) ( 6 \times 1 0 ^{- 15} )}{50 \times 1 0 ^{- 9}} = 2.763 \times 1 0^{- 18} F$

Delays (use $t = R C$ , arbitrary units of seconds): $t_{A} = R_{A} C_{A} = 900 \times 4.144 \times 1 0^{- 18} = 3.730 \times 1 0^{- 15} s$ $t_{B} = R_{B} C_{B} = 566.67 \times 2.763 \times 1 0^{- 18} = 1.566 \times 1 0^{- 15} s$ $\frac{t _{A}}{t _{B}} = \frac{3.730}{1.566} = 2.382$ Option B is about 2.38× faster on this wire.

L4.2 — Delay is $t = R C = (ρ \frac{L}{A}) (k ε_{0} \frac{A _{cap}}{d})$ . Every geometric term ( $L, A, A_{cap}, d, ε_{0}$ ) is identical between A and B, so it cancels in the ratio. Only $ρ$ and $k$ differ: $\frac{t _{A}}{t _{B}} = \frac{ρ _{A}}{ρ _{B}} \cdot \frac{k _{A}}{k _{B}} = \frac{2.7}{1.7} \cdot \frac{3.9}{2.6} = 1.588 \times 1.5 = 2.382 ✓$ The improvement is the product because $R$ carries the $ρ$ ratio and $C$ carries the $k$ ratio, and delay multiplies them. That is the whole "copper and low-k" strategy in one line.

Level 5 — Mastery

L5.1 — An engineer proposes replacing the Ta/TaN barrier with a thicker barrier to "be safe." The barrier has resistivity far higher than copper, and it eats into the trench, leaving less room for copper. If a $50 nm$ -wide trench gets a barrier that is $8 nm$ thick on each sidewall, what copper width remains, and by what factor does the copper's resistance rise versus a barrier-free $50 nm$ fill (assume $H$ unchanged, and treat only the copper as conducting)?

L5.2 — Given the L5.1 result, argue why barrier thinning (not thickening) is a major research theme, yet why the barrier can never be removed entirely. Tie it to two failure modes.

Recall Solution — L5

L5.1 — A barrier of $8 nm$ on each sidewall removes $2 \times 8 = 16 nm$ from the fillable width: $W_{Cu} = 50 - 16 = 34 nm$ Resistance $\propto 1/ W$ (with $H$ fixed and treating only copper as conducting), so: $\frac{R _{barrier}}{R _{full}} = \frac{50}{34} = 1.471$ The copper's resistance rises by ~1.47× (~47% worse) purely from the space the barrier steals. On a $50 nm$ wire, a "thick to be safe" barrier is self-defeating — you lose most of the copper advantage you paid for.

L5.2 — Why thin the barrier: as L5.1 shows, every nanometre of barrier is a nanometre stolen from copper, and at nanoscale that stolen fraction is huge (16 of 50 nm ⇒ 32% of the width gone). Thinner barrier ⇒ more copper ⇒ lower $R$ ⇒ lower $R C$ delay. This ties to Physical Vapor Deposition and electroplating (getting a conformal, ultra-thin barrier + seed into a nanoscale trench) and RC delay and interconnect scaling.

Why the barrier can never vanish: it prevents two failure modes. (1) Copper diffusion: bare copper drifts into the silicon and dielectric, creating deep-level traps that destroy transistor behaviour — a poison you cannot undo (see Front-End-Of-Line (FEOL) transistor formation). (2) Electromigration / adhesion loss: the barrier also anchors the copper and blocks the atom transport that drives Electromigration and reliability failures. So the barrier must be as thin as possible but never zero — a genuine engineering optimum.

Recall Master checklist — cover and recite

BEOL vs FEOL, and the temperature reason ::: Metallization is BEOL; metals melt/diffuse at ~1000 °C FEOL anneals, so wiring comes after.
The two equations and what each symbol means ::: $R = ρ L / (W H)$ , $C = k ε_{0} A / d$ ; delay is their product $R C$ .
Why improvements from Cu and low-k multiply ::: Delay $= R C$ ; $ρ$ lives in $R$ , $k$ lives in $C$ , so ratios multiply.
Why scaling hurts wires (8× in L3.2) ::: Smaller $W, H$ raise $R$ ; smaller $d$ raises $C$ ; both worsen $R C$ .
The barrier's real cost and its two failure modes it prevents ::: It steals copper width (raises $R$ ) but must stay to stop Cu diffusion and aid EM/adhesion.