Metallization and interconnect layers: Worked examples

This is a deep-dive drill page for Metallization and interconnect layers. We take the two master formulas from the parent note — wire resistance and wire capacitance — and push them through every kind of input you could meet: normal numbers, extreme geometries, zero and degenerate cases, limiting behaviour, a real-world word problem, and an exam-style twist.

Everything is built from just two equations. Let us re-earn them before using any symbol.

The two tools, re-derived from zero

The scenario matrix

Every problem this topic throws is one of these cells. The worked examples below each carry a [Cell] tag so you can see the whole grid is covered.

#	Cell (what makes it special)	Which tool	Covered by
A	Plain, in-range numbers	$R = ρ L / W H$	Ex 1
B	Same wire, only material changes (ratio)	$R \propto ρ$	Ex 2
C	Geometry scaling — shrink width by half	$R \propto 1/ W$	Ex 3
D	Degenerate: $W \to 0$ (limiting behaviour)	limit of $R$	Ex 4
E	Zero / open case: $L = 0$ or infinite gap $d \to \infty$	$R \to 0$ , $C \to 0$	Ex 5
F	Capacitance ratio, only $k$ changes	$C \propto k$	Ex 6
G	Full $R C$ delay — both tools together, units	$R C$	Ex 7
H	Real-world word problem: power grid line	$R$ , $P$	Ex 8
I	Exam twist: fixed cross-section, split into two layers	series/parallel $R$	Ex 9
J	Exam twist: "which improves delay more, Cu or low-k?"	compare $R C$	Ex 10

Worked examples

Worked example Ex 1 — [Cell A] Plain resistance

A copper Metal-1 line: $L = 100 μ m$ , $W = 50 nm$ , $H = 100 nm$ , $ρ_{Cu} = 1.7 \times 1 0^{- 8} Ω \cdot m$ . Find $R$ .

Forecast: guess — will it be milliohms, ohms, or hundreds of ohms? (These wires are astonishingly thin.)

Convert every length to metres: $L = 100 \times 1 0^{- 6}$ , $W = 50 \times 1 0^{- 9}$ , $H = 100 \times 1 0^{- 9}$ . Why this step? The formula only gives correct ohms if every quantity is in SI base units; mixing µm and nm silently breaks it.
Cross-section: $A = W H = 50 \times 1 0^{- 9} \times 100 \times 1 0^{- 9} = 5 \times 1 0^{- 15} m^{2}$ . Why this step? Current flows through the sliced face; that face is the $W \times H$ rectangle.
$R = ρ \frac{L}{A} = \frac{1.7 \times 1 0 ^{- 8} \times 100 \times 1 0 ^{- 6}}{5 \times 1 0 ^{- 15}} = 340 Ω$ . Why this step? Direct substitution — length on top, area on bottom.

Verify: units $\frac{( Ω \cdot m ) ( m )}{m ^{2}} = Ω$ ✓. A single hair-thin wire is already hundreds of ohms — that is exactly why RC delay dominates advanced nodes.

Worked example Ex 8 — [Cell H] Real-world word problem: a power line and its heat

An upper-layer copper power rail carries $I = 2 mA$ and has resistance $R = 50 Ω$ . How much power does it waste as heat, and why do designers make power rails wide?

Forecast: microwatts or milliwatts?

Power dissipated in a resistor: $P = I^{2} R$ . Why this step? Heat in a wire depends on current squared times resistance — this is the Joule-heating law, the tool for "how hot / how lossy."
$P = (2 \times 1 0^{- 3})^{2} \times 50 = 4 \times 1 0^{- 6} \times 50 = 2 \times 1 0^{- 4} W = 0.2 mW$ .
To cut this, lower $R$ ; since $R \propto 1/ (W H)$ , widen and thicken the rail. Why this step? Connects the answer back to the design rule — upper metals are thick precisely to carry power with low loss and to survive electromigration.

Verify: units $A^{2} \cdot Ω = A^{2} \cdot \frac{V}{A} = A \cdot V = W$ ✓. $0.2 mW$ per rail × millions of rails = the reason power delivery is a whole engineering discipline.

Worked example Ex 9 — [Cell I] Exam twist: split one wire into two half-height layers in parallel

A wire of cross-section $W \times H$ is instead built as two stacked wires each of height $H /2$ , carrying the same current in parallel (same $L$ , same $ρ$ , same total footprint). Show the combined resistance equals the original.

Forecast: higher, lower, or identical to the single wire?

Each half-wire: $R_{half} = ρ \frac{L}{W ( H /2 )} = 2 ρ \frac{L}{W H} = 2 R$ . Why this step? Halving height halves area, doubling each piece's resistance.
Two equal resistors in parallel: $R_{tot} = \frac{R _{half}}{2} = \frac{2 R}{2} = R$ . Why this step? Parallel resistors of equal value $R_{p}$ combine to $R_{p} /2$ ; the doubling and the halving cancel.

Verify: with $R = 340 Ω$ : each half $= 680 Ω$ , parallel of two gives $\frac{680}{2} = 340 Ω$ ✓. Lesson: it is the total conducting area that sets resistance, not how you slice it — a favourite trap on exams.

Worked example Ex 10 — [Cell J] Exam twist: Cu or low-k, which helps delay more here?

A wire currently has $R = 540 Ω$ (aluminium) and $C = 0.30 fF$ in $SiO_{2}$ ( $k = 3.9$ ). Option 1: switch to copper (drop $R$ to $340 Ω$ ). Option 2: switch to low-k $k = 2.5$ (drop $C$ to $0.30 \times \frac{2.5}{3.9}$ ). Which gives the smaller RC delay?

Forecast: guess which single swap wins before computing.

Baseline delay: $τ_{0} = 540 \times 0.30 \times 1 0^{- 15} = 1.62 \times 1 0^{- 13} s$ . Why this step? We need a reference so both options are compared to the same starting point.
Option 1 (copper): $τ_{1} = 340 \times 0.30 \times 1 0^{- 15} = 1.02 \times 1 0^{- 13} s$ . Ratio $\frac{340}{540} = 0.630$ .
Option 2 (low-k): new $C = 0.30 \times 0.641 = 0.192 fF$ ; $τ_{2} = 540 \times 0.192 \times 1 0^{- 15} = 1.038 \times 1 0^{- 13} s$ . Ratio $\frac{2.5}{3.9} = 0.641$ . Why this step? Because delay scales with whichever factor drops most, we compare the two fractional drops directly.
Copper wins here ( $0.630 < 0.641$ ), but only barely. Why this step? The honest exam answer: it depends on the numbers — in this case the resistivity drop (2.7→1.7) is slightly bigger than the $k$ drop (3.9→2.5), so copper edges it. Real chips do both.

Verify: $τ_{1} = 1.02 \times 1 0^{- 13}$ vs $τ_{2} = 1.038 \times 1 0^{- 13}$ ✓, and both beat $τ_{0} = 1.62 \times 1 0^{- 13}$ ✓. Neither swap alone is enough — the parent note's conclusion "copper and low-k" is exactly why.

Figure — Metallization and interconnect layers

The figure above traces the whole matrix on one plot: resistance vs wire width (Cell C/D — the curve blowing up as $W \to 0$ ), with the amber markers showing Ex 1 and Ex 3, and the dashed cyan line marking the aluminium level from Ex 2.

This second figure is the Ex 9 geometry: one solid wire versus the same footprint split into two half-height wires in parallel — showing why the total resistance is unchanged.

Recall Active recall — cover the answers

Which cell shows R going to infinity, and why? ::: Cell D ( $W \to 0$ ): area vanishes so $R \propto 1/ W \to \infty$ . Halving a wire's width does what to R? ::: Doubles it, since $R \propto 1/ W$ (Ex 3). Splitting a wire into two half-height parallel wires changes R how? ::: Not at all — total conducting area is what matters (Ex 9). In Ex 10, why does copper barely beat low-k? ::: The resistivity ratio 1.7/2.7 = 0.63 is slightly smaller than the k ratio 2.5/3.9 = 0.641. Units of the RC product? ::: Ohm × farad = seconds.