Noesis
Level 2 — RecallSemiconductor Fabrication

Semiconductor Fabrication

⏱ 30 minutes50 marksprintable — key stays hidden on paper

Level: 2 (Recall / Standard textbook problems) Time limit: 30 minutes Total marks: 50

Section A — Short Answer

Q1. Define the Czochralski process and name the two key items produced from it before wafers are cut. (4 marks)

Q2. Explain the difference between positive and negative photoresist in terms of what happens to the exposed region during development. (4 marks)

Q3. State two differences between wet etching and dry (plasma) etching. Which one generally gives better anisotropy (vertical sidewalls)? (5 marks)

Q4. In one line each, define: (a) CVD, (b) PVD/sputtering, (c) ALD. State which of these gives the best atomic-level thickness control. (6 marks)

Q5. Describe the copper damascene process in ordered steps (trench etch → ... → CMP). List at least four steps. (5 marks)

Section B — Standard Problems

Q6. The Rayleigh criterion for lithography resolution is: R=k1λNAR = k_1 \frac{\lambda}{NA} Given k1=0.30k_1 = 0.30, wavelength λ=193 nm\lambda = 193\text{ nm} (DUV) and NA=1.35NA = 1.35, compute the minimum resolvable feature size RR in nm (2 decimal places). (5 marks)

Q7. Repeat the calculation for EUV with λ=13.5 nm\lambda = 13.5\text{ nm}, k1=0.30k_1 = 0.30, NA=0.33NA = 0.33. State which technology resolves smaller features. (5 marks)

Q8. A wafer process has a defect density D0=0.5 defects/cm2D_0 = 0.5\ \text{defects/cm}^2 and a die area A=1 cm2A = 1\ \text{cm}^2. Using the simple Poisson yield model Y=e−D0AY = e^{-D_0 A}, compute the yield YY (3 decimal places) and express as a percentage. (5 marks)

Q9. Briefly explain why multi-patterning (e.g. LELE double patterning) was needed at advanced nodes when using 193 nm DUV lithography. (4 marks)

Q10. Compare FinFET and Gate-All-Around (GAA) nanosheet transistors: state how many sides the gate controls the channel from in each case. (7 marks)

End of paper

Answer keyMark scheme & solutions

Q1. (4 marks)

  • Czochralski process: a method of growing a single-crystal silicon ingot (boule) by dipping a seed crystal into molten silicon and slowly pulling/rotating it while it solidifies. (2)
  • Key items produced: the single-crystal ingot/boule, and the seed crystal used to set orientation. (2) Why: pulling a seed from the melt propagates the crystal orientation, giving monocrystalline silicon for wafers.

Q2. (4 marks)

  • Positive resist: exposed region becomes soluble and is washed away → pattern matches the clear areas of the mask. (2)
  • Negative resist: exposed region cross-links/hardens and stays; unexposed washes away → pattern is the inverse. (2)

Q3. (5 marks)

  • Wet etch = liquid chemical, isotropic, cheaper, high selectivity; Dry/plasma = gas/ions, anisotropic, better for fine features. (2 per valid difference, max 4)
  • Dry (plasma) etching gives better anisotropy. (1)

Q4. (6 marks)

  • (a) CVD: film grown by chemical reaction of gaseous precursors on the wafer surface. (1.5)
  • (b) PVD/sputtering: material physically ejected from a target by ion bombardment and deposited on the wafer. (1.5)
  • (c) ALD: film grown one atomic monolayer at a time via self-limiting surface reactions. (1.5)
  • Best atomic-level control: ALD. (1.5)

Q5. (5 marks) Ordered steps (any 4, in order):

  1. Deposit/pattern dielectric and etch trench/via.
  2. Deposit barrier/liner (e.g. Ta/TaN) + Cu seed.
  3. Electroplate copper to fill trench (overfill).
  4. CMP to remove excess Cu and planarize. (≈1.25 per correct ordered step) Why damascene: Cu is hard to plasma-etch, so metal is inlaid into etched dielectric instead.

Q6. (5 marks) R=0.30×1931.35=0.30×142.96=42.89 nmR = 0.30 \times \frac{193}{1.35} = 0.30 \times 142.96 = 42.89\text{ nm}

  • Correct substitution (2), division 193/1.35=142.96193/1.35=142.96 (1), final R≈42.89R \approx 42.89 nm (2).

Q7. (5 marks) R=0.30×13.50.33=0.30×40.91=12.27 nmR = 0.30 \times \frac{13.5}{0.33} = 0.30 \times 40.91 = 12.27\text{ nm}

  • Substitution (2), division (1), final R≈12.27R \approx 12.27 nm (1).
  • EUV resolves much smaller features. (1)

Q8. (5 marks) Y=e−D0A=e−0.5×1=e−0.5=0.607Y = e^{-D_0 A} = e^{-0.5 \times 1} = e^{-0.5} = 0.607

  • D0A=0.5D_0 A = 0.5 (1), e−0.5=0.6065e^{-0.5}=0.6065 (2), rounded 0.6070.607 (1) → 60.7% (1).

Q9. (4 marks)

  • 193 nm DUV resolution is limited by the Rayleigh criterion; feature pitches shrank below what a single exposure could resolve. (2)
  • Multi-patterning splits a dense pattern into two or more exposures/masks so each is within the tool's resolution, effectively halving the pitch. (2)

Q10. (7 marks)

  • FinFET: gate wraps the fin on 3 sides (two sidewalls + top). (2)
  • GAA nanosheet: gate surrounds the channel on all 4 sides (fully surrounds each nanosheet). (2)
  • GAA gives better electrostatic control / lower leakage, enabling scaling beyond FinFET; stacked nanosheets tune drive current. (3)
[
  {"claim":"DUV resolution R = 0.30*193/1.35 ≈ 42.89 nm","code":"R=Rational(30,100)*193/Rational(135,100); result = abs(float(R)-42.89)<0.01"},
  {"claim":"EUV resolution R = 0.30*13.5/0.33 ≈ 12.27 nm","code":"R=Rational(30,100)*Rational(135,10)/Rational(33,100); result = abs(float(R)-12.27)<0.01"},
  {"claim":"Poisson yield Y=e^{-0.5} ≈ 0.607","code":"Y=exp(Rational(-1,2)); result = abs(float(Y)-0.607)<0.001"},
  {"claim":"EUV feature smaller than DUV feature","code":"duv=0.30*193/1.35; euv=0.30*13.5/0.33; result = euv<duv"}
]