FEOL aur BEOL alag KYU hain? Transistors ko high-temperature steps chahiye hote hain (implant anneal ~1000 °C). Aluminum/copper jaise metals un temperatures par pighal jaate hain ya diffuse ho jaate hain, isliye wiring baad mein hoti hai jab saare hot device steps khatam ho jaate hain.
Wire ka resistance:
R=ρAL=ρWHL
jahaan ρ = resistivity, L = length, W = width, H = height (cross-section A=WH).
KYU copper jeeta hai:ρCu≈1.7μΩ⋅cm vs ρAl≈2.7μΩ⋅cm. Kam ρ ⇒ kam R ⇒ faster, thande chips. Copper electromigration (atoms ka high current ke under drift karna, jo aluminum wires ko tod deta hai) ko bhi kaafi zyada resist karta hai.
Lekin — copper ko plasma se asaani se etch nahi kiya ja sakta (iski halides volatile nahi hoti). Isliye ek alag trick use ki jaati hai: damascene process.
"Metal deposit karo → usse wires mein etch karo" ke bajaye, damascene ulta karta hai: "dielectric mein trenches khodho → copper se bharo → flat polish karo."
Dielectric deposit karo (ILD) surface ke upar.
Trenches/vias etch karo dielectric mein jahaan wires jaani chahiye (lithography se pattern kiya hua).
Barrier layer deposit karo (e.g. Ta/TaN) — KYU? Copper silicon/dielectric mein diffuse ho jaata hai aur transistors ko poison karta hai; barrier ek wall hai jo ise rokti hai.
Copper seed layer deposit karo, phir trenches ko overfill karne ke liye electroplate copper karo.
CMP (Chemical-Mechanical Planarization): trenches ke upar baitha copper grind/polish karke hata do, copper sirf trenches ke andar rehta hai — bilkul flat.
Kam resistivity (~1.7 vs 2.7 µΩ·cm) aur better electromigration resistance.
Why can't copper be plasma-etched into wires?
Iski etch by-products (halides) volatile nahi hain, isliye subtractive etching kaam nahi karti — isliye damascene use hota hai.
What is the damascene process in one line?
Dielectric mein trenches etch karo, copper se bharo, phir CMP se flat karo (inlay/additive).
What is dual damascene?
Via + trench etch karna aur dono ko ek deposition + ek CMP step mein copper se bharna.
Main purpose of the barrier layer (e.g. Ta/TaN)?
Copper diffusion ko silicon/dielectric mein block karna (adhesion bhi help karta hai).
What does CMP stand for and do?
Chemical-Mechanical Planarization — overfill metal polish karke hata deta hai, flat surface chhod jaata hai.
Why use a low-k dielectric?
Inter-wire capacitance C=kε0A/d kam karta hai, RC delay aur dynamic power reduce karta hai.
What is a via vs a contact?
Via do metal layers ko connect karta hai; contact Metal-1 ko transistor silicon se neeche connect karta hai.
What dominates delay in advanced nodes, gate delay or RC interconnect delay?
Interconnect RC delay increasingly dominant hoti jaati hai, Cu + low-k adoption ko drive karti hai.
Recall Feynman: 12-saal ke bacche ko samjhao
Socho tumne tiny light-switches (transistors) ka ek sheher banaya lekin wires bhool gaye. Metallization woh hai jab saari wires aur connectors lagate hain. Purani wires aluminum ki hoti thi, lekin engineers ne paaya ki copper wires mein electricity zyada fast chalti hai aur jaldi ghisti nahi. Copper ko patli wires mein kaatna mushkil hai, isliye woh ek glass-jaisi layer mein tiny naliyan khodh te hain, unme copper bharte hain, aur upar smooth polish kar dete hain — jaise floor ki daraaron ko metal se bharna aur phir sand karna. Woh in wires ke kai floors stack karte hain taaki laakhon connections kabhi ek doosre se na takraayein.
