Semiconductor Fabrication

Q1 (12)

(a) Rayleigh: $\text{half-pitch} = k_1 \dfrac{\lambda}{NA}$. (1)

• $\lambda$ = exposure wavelength; $NA$ = numerical aperture of projection lens ($= n\sin\theta$); $k_1$ = process-dependent constant (theoretical floor 0.25 for single exposure). (2)

(b) $HP = 0.28 \times \dfrac{193}{1.35} = 0.28 \times 142.96 = 40.0\,\text{nm}$. (3) (accept ~40 nm)

(c) $HP = 0.4 \times \dfrac{13.5}{0.33} = 0.4 \times 40.91 = 16.4\,\text{nm}$. (2) Explain: EUV's ~14× shorter wavelength gives a far smaller $\lambda/NA$ even at higher $k_1$ and modest $NA$, so a single EUV exposure resolves features that DUV can only reach by splitting the pattern across multiple masks/etch steps (multi-patterning) — cutting mask count, cost, and overlay error. (2)

(d) $DOF = k_2 \lambda / NA^2$: resolution scales as $1/NA$ but DOF scales as $1/NA^2$. (1) So raising $NA$ sharpens resolution but shrinks the usable focus window quadratically, tightening flatness/CMP and wafer-stage tolerances. (1)

Q2 (12)

(a) Three fluxes in steady state ($F_1=F_2=F_3=F$): (1 setup)

• Gas→surface: $F_1 = h(C^* - C_0)$
• Diffusion through oxide: $F_2 = D\dfrac{C_0 - C_i}{x_o}$
• Interface reaction: $F_3 = k_s C_i$ (2)

Set equal and solve: from $F=k_s C_i$ and $F=D(C_0-C_i)/x_o$ and $F=h(C^*-C_0)$, eliminate $C_0,C_i$: $F = \frac{C^*}{\frac{1}{k_s} + \frac{1}{h} + \frac{x_o}{D}}$ (2) Growth rate $\dfrac{dx_o}{dt} = F/N$ ($N$ = oxidant atoms per unit oxide volume). Integrate: $x_o^2 + A x_o = B(t+\tau)$ (1) with $A = 2D\left(\tfrac1{k_s}+\tfrac1h\right)$, $B = \dfrac{2DC^*}{N}$, $\tau = \dfrac{x_i^2 + A x_i}{B}$ (accounts for initial oxide). (1)

(b) Long $t$: $x_o^2 \gg A x_o \Rightarrow x_o^2 \approx Bt \Rightarrow x_o\approx\sqrt{Bt}$ (parabolic, diffusion-limited). (1.5) Short $t$: $A x_o \gg x_o^2 \Rightarrow x_o \approx \dfrac{B}{A}(t+\tau)$ (linear, reaction-limited). $B/A$ = linear rate constant. (1.5)

(c) Oxygen must reach the Si interface and react, converting Si into SiO₂, so the interface moves into the wafer. (1) Si consumed $= 0.44 \times 100 = 44\,\text{nm}$. (1)

Q3 (10)

(a) Defects fall randomly and independently; number on a die of area $A$ is Poisson with mean $\lambda = D_0 A$. Yield = P(0 killer defects) $= e^{-\lambda} = e^{-D_0 A}$. (2)

(b) $Y(2) = e^{-0.15\times2} = e^{-0.3} = 0.741$ (74.1%). (1.5) $Y(4) = e^{-0.15\times4} = e^{-0.6} = 0.549$ (54.9%). (1.5)

(c) Yield decays exponentially with area, so loss $(1-Y)$ grows faster than linearly for large $A$ (compounding). Doubling area squares the survival probability: $Y(2A)=Y(A)^2$, so more than double the loss fraction. (2) Chiplets split a big SoC into small high-yield dies; binning sells partially-defective dies at lower spec (disable a core/lower clock) rather than scrapping. (1)

(d) Wafer area $= \pi (15\,\text{cm})^2 = 706.86\,\text{cm}^2$. Gross dies $= 706.86/2 \approx 353$. (1) Good dies $\approx 353 \times 0.741 \approx 262$. (1)

Q4 (8)

(a) Dual-damascene sequence: (3, deduct 0.5 per misordering)

1. Deposit ILD (dielectric, e.g. low-k oxide).
2. Pattern & etch via holes (lithography + dry etch).
3. Pattern & etch trenches (metal-line pattern).
4. Deposit barrier/liner (TaN/Ta).
5. Deposit Cu seed (PVD) then electroplate Cu to overfill trench+via.
6. Anneal.
7. CMP to remove overburden, leaving inlaid Cu lines/vias. Cu has no volatile etch byproduct at reasonable temperature (halides non-volatile), so subtractive plasma etch of Cu is impractical → deposit-then-polish (damascene) instead. (2)

(b) Barrier/liner (Ta/TaN) blocks Cu diffusion into the dielectric (Cu is a fast diffuser and poisons Si/oxide) and improves adhesion. (1.5) CMP removes the overfilled Cu/barrier overburden and planarizes each layer so the next lithography level has a flat, in-focus surface. (1.5)

Q5 (10)

(a) In short-channel planar MOSFETs the drain field increasingly controls the channel (DIBL, punch-through, poor subthreshold slope); single-side gate loses electrostatic control → high leakage. (3)

(b) (4, 1.33 each)

• Geometry: FinFET gate wraps 3 sides of a fin; GAA wraps all 4 sides of stacked nanosheets → better electrostatic control, lower leakage.
• Effective width: FinFET width is quantized (add whole fins); GAA tunes width by nanosheet width → finer design granularity.
• Drive current/footprint: GAA stacks multiple sheets vertically → higher $W_{eff}$/drive per footprint at advanced nodes.

(c) Double-gate fin: each fin contributes conduction on two sidewalls plus top (approx): $W_{eff}\approx n(2H_{fin}+W_{fin})$. (1) $W_{eff} = 3(2\times50 + 7) = 3\times107 = 321\,\text{nm}$. (2) (Accept $W_{eff}=n\cdot2H_{fin}=300$ nm for pure double-gate.)

Q6 (8)

import math
def ald_thickness(gpc_nm, target_nm):
    return math.ceil(target_nm / gpc_nm)          # cycles, rounded up
 
def ald_time(gpc_nm, target_nm, t_cycle_s):
    return ald_thickness(gpc_nm, target_nm) * t_cycle_s

(4 for correct code incl. ceil, 1 for time extension)

Explain: each ALD cycle = self-limiting half-reactions (precursor dose saturates surface, then co-reactant). Once all surface sites react, no further growth that pulse — so exactly one monolayer-fraction (GPC) deposits per cycle regardless of dose. Hence thickness $= GPC \times \text{cycles}$ (linear), giving atomic-level, conformal control. (3)

[
  {"claim":"DUV half-pitch ~40nm", "code":"hp=0.28*193/1.35; result = abs(hp-40.0)<0.5"},
  {"claim":"EUV half-pitch ~16.4nm", "code":"hp=0.4*13.5/0.33; result = abs(hp-16.36)<0.2"},
  {"claim":"Yields 74.1% and 54.9%", "code":"from sympy import exp,N; y2=N(exp(-0.3)); y4=N(exp(-0.6)); result = abs(y2-0.7408)<0.001 and abs(y4-0.5488)<0.001"},
  {"claim":"Wafer gross die ~353 and good ~262", "code":"from sympy import pi,exp,N; area=N(pi*15**2); gross=int(area/2); good=int(gross*N(exp(-0.3))); result = gross==353 and 260<=good<=263"},
  {"claim":"FinFET Weff=321nm", "code":"n=3;H=50;W=7; result = n*(2*H+W)==321"}
]