FinFET transistor structure

WHAT is a FinFET?

Key geometric parts:

Fin: the thin, tall strip of silicon carrying the channel. Its height $H_{fin}$ and width $W_{fin}$ set the device size.
Gate: wraps the fin; the gate length $L_g$ runs along the fin.
Source / Drain: the two ends of the fin, heavily doped.
Gate oxide: thin insulator between gate and fin.

WHY did we need it? (Steel-manning the planar MOSFET)

The electrostatic reason (derived)

The gate controls the channel over a distance called the natural length $\lambda$ . Short-channel effects become bad when $L_g \lesssim (\text{a few}) \times \lambda$ . We derive $\lambda$ from Poisson's equation in a simplified channel.

Setup (WHY these steps): In the depleted channel, the potential $\psi(x,y)$ obeys Poisson's equation. We assume the vertical potential profile is roughly parabolic across the silicon body (a standard, physically-motivated approximation — the gate sets boundary conditions on the surfaces). Integrating Poisson's equation across the body converts the 2D problem into a 1D equation along the channel:

$\frac{d^2 \psi_c(y)}{dy^2} - \frac{\psi_c(y) - \psi_{gate}}{\lambda^2} = 0$

The parameter $\lambda$ that emerges is the natural length:

$\boxed{\;\lambda = \sqrt{\frac{\varepsilon_{si}}{\alpha\,\varepsilon_{ox}}\, t_{si}\, t_{ox}}\;}$

where:

$\varepsilon_{si},\varepsilon_{ox}$ = permittivities of silicon and oxide,
$t_{si}$ = silicon body thickness (for a fin, the fin width $W_{fin}$ ... but only the part gated),
$t_{ox}$ = gate-oxide thickness,
$\alpha$ = number of gates: $\alpha=1$ (single/planar), $2$ (double-gate), $\approx 3$ (triple-gate/FinFET).

Design rule of thumb: to keep SCE tolerable you want roughly $L_g \gtrsim 5\text{–}6\,\lambda.$ So halving $\lambda$ lets you halve $L_g$ ⇒ smaller, denser chips.

HOW does current scale? (Effective width)

Deriving the effective width $W_{eff}$ per fin (WHY: current flows along each conducting surface, so widths add):

$W_{eff} = \underbrace{2 H_{fin}}_{\text{two sidewalls}} + \underbrace{W_{fin}}_{\text{top}}$

For a tall, thin fin, $H_{fin}\gg W_{fin}$ , so $W_{eff}\approx 2H_{fin}$ .

Worked Examples

Worked example

Example 1 — Natural length, planar vs FinFET. Given $\varepsilon_{si}=11.7\varepsilon_0$ , $\varepsilon_{ox}=3.9\varepsilon_0$ , $t_{si}=10\text{ nm}$ , $t_{ox}=1\text{ nm}$ .

Planar ( $\alpha=1$ ): $\lambda = \sqrt{\frac{11.7}{1\cdot 3.9}\cdot 10\cdot 1}\ \text{nm} = \sqrt{3\cdot 10}\ \text{nm}=\sqrt{30}\approx 5.5\text{ nm}.$ Why this step? The $\varepsilon_0$ cancels in the ratio, leaving relative permittivities.

FinFET ( $\alpha=3$ ): $\lambda = \sqrt{\frac{11.7}{3\cdot 3.9}\cdot 10\cdot 1}\ \text{nm}=\sqrt{1\cdot10}=\sqrt{10}\approx 3.2\text{ nm}.$ Interpretation: the triple-gate cuts $\lambda$ by $\sqrt{3}\approx1.73\times$ . With the $L_g\gtrsim5\lambda$ rule, planar needs $L_g\gtrsim 27$ nm but the FinFET works down to $\gtrsim 16$ nm. That's the whole reason FinFETs exist.

Common Mistakes

Flashcards

What geometric change defines a FinFET vs a planar MOSFET?

The channel is a thin vertical silicon fin and the gate wraps it on three sides (top + two sidewalls), instead of a flat gate on top of a planar channel.

Why were FinFETs introduced as

L_g

shrank?

To suppress short-channel effects / DIBL / leakage: the multi-sided gate gives stronger electrostatic control so the transistor can fully switch OFF at small gate lengths.

Write the natural length formula and state what small

\lambda

means.

\lambda=\sqrt{\varepsilon_{si}t_{si}t_{ox}/(\alpha\varepsilon_{ox})}

; small

\lambda

= better immunity to short-channel effects (gate keeps control at shorter

L_g

Three ways a FinFET reduces

\lambda

vs planar?

Thin fin (small

t_{si}

), thin oxide (small

t_{ox}

), more gates (

\alpha\approx3

vs 1).

Effective width of one fin?

W_{eff}=2H_{fin}+W_{fin}\approx 2H_{fin}

for tall thin fins.

Why is FinFET width "quantized"?

Current flows on the surfaces of whole fins; you add current in units of one fin, so total width =

N(2H_{fin}+W_{fin})

Should fins be wide or narrow, and why?

Narrow — a thin fin lowers

t_{si}

\lambda

, improving gate control and reducing leakage.

Roughly how does

L_g

relate to

\lambda

for good behavior?

L_g \gtrsim 5\text{–}6\lambda

What does

\alpha

represent in the

\lambda

formula?

The number of gate surfaces controlling the channel (1 planar, 2 double-gate, ~3 FinFET, 4 GAA).

What is the successor to FinFET that increases

\alpha

further?

Gate-All-Around (GAA) / nanosheet transistors,

\alpha\to4

(gate surrounds channel on all sides).

Recall Feynman: explain to a 12-year-old

Imagine a garden hose (the channel) that water flows through when you let it. The tap (the gate) turns it on and off. In old transistors the tap only pressed on the top of the hose — when hoses got tiny, the tap couldn't fully squeeze it shut and water leaked. The FinFET stands the hose up like a thin wall and squeezes it from three sides at once, so it shuts off completely. Standing it up tall also lets more water flow — you get the same strong hose using less floor space. Thin and tall = the winning shape.

Connections

Planar MOSFET — the predecessor FinFET improves on.
Short-Channel Effects and DIBL — the problems FinFETs solve.
Gate-All-Around Transistor (GAA / nanosheet) — the next step, $\alpha\to4$ .
Poisson's Equation in MOS Electrostatics — origin of natural length $\lambda$ .
Moore's Law and Dennard Scaling — why we kept shrinking $L_g$ .
Gate Oxide and High-k Dielectrics — the $t_{ox}$ term in $\lambda$ .

Concept Map

Hinglish (regional understanding)

Intuition Hinglish mein samjho

Dekho, purana planar MOSFET ek flat road jaisa hai jisme gate upar se sirf ek side se channel ko control karta hai. Jab transistor bahut chhota (small $L_g$ ) ho gaya, to gate akela channel ko OFF nahi kar pa raha tha — drain ka electric field andar ghus jata hai. Isko bolte hain short-channel effect aur leakage. Matlab OFF karne par bhi current beh raha hai — power waste, heat problem.

FinFET ka jugaad simple hai: channel ko ek patli, khadi silicon deewar (fin) bana do, aur gate ko uske teen taraf (top + do sidewalls) lapet do. Ab gate ki grip 3 side se hai, isliye control bahut strong. Iska maths natural length $\lambda=\sqrt{\varepsilon_{si}\,t_{si}\,t_{ox}/(\alpha\,\varepsilon_{ox})}$ me dikhta hai — $\lambda$ jitna chhota, utna acha. FinFET teeno cheezein deta hai: patli fin ( $t_{si}$ chhota), patli oxide ( $t_{ox}$ chhota), aur teen gates ( $\alpha\approx3$ ). Isliye $\lambda$ girta hai aur hum $L_g$ aur chhota bana sakte hain.

Current ke liye ek aur mazedaar baat: current fin ke dono sidewalls aur top par behta hai, isliye effective width $W_{eff}=2H_{fin}+W_{fin}$ . Fin ko tall banao to zyada current milta hai bina extra chip area liye. Ek yaad rakhne wali cheez: fin ko patli rakhna hai (leakage kam), lekin lambi (current zyada) — "Thin, Tall, Tri-gate". Aur haan, width quantized hoti hai — poore fins ke units me hi milti hai, beech ka fractional fin nahi.

Yeh important isliye hai kyunki Moore's Law ko chalane ke liye 22nm ke aas-paas industry ko FinFET pe shift hona pada, warna leakage se chip garam ho jati aur scaling ruk jati. Aage ka step GAA/nanosheet hai jisme gate 4 side se ( $\alpha\to4$ ) lapetta hai.

WHAT is a FinFET?

WHY did we need it? (Steel-manning the planar MOSFET)

The electrostatic reason (derived)

HOW does current scale? (Effective width)

Worked Examples

Common Mistakes

Flashcards

Connections

Concept Map

Hinglish (regional understanding)

Go deeper — visual, from zero

Test yourself — Semiconductor Fabrication

Connections