FinFET transistor structure — Hinglish notes

4.3.19 · Hardware › Semiconductor Fabrication

WHAT is a FinFET?

Key geometric parts:

Fin: silicon ki patli, lambi strip jo channel carry karti hai. Iska height $H_{f in}$ aur width $W_{f in}$ device size set karte hain.
Gate: fin ko wrap karta hai; gate length $L_{g}$ fin ke saath-saath chalta hai.
Source / Drain: fin ke do ends, heavily doped.
Gate oxide: gate aur fin ke beech patla insulator.

WHY did we need it? (Steel-manning the planar MOSFET)

The electrostatic reason (derived)

Gate channel ko ek distance pe control karta hai jise natural length $λ$ kehte hain. Short-channel effects tab kharab hote hain jab $L_{g} ≲ (kuch) \times λ$ . Hum $λ$ ko channel mein simplified Poisson's equation se derive karte hain.

Setup (WHY these steps): Depleted channel mein, potential $ψ (x, y)$ Poisson's equation follow karta hai. Hum assume karte hain ki silicon body mein vertical potential profile roughly parabolic hai (ek standard, physically-motivated approximation — gate surfaces par boundary conditions set karta hai). Body ke across Poisson's equation ko integrate karne se 2D problem ek 1D equation mein convert ho jaati hai channel ke along:

$\frac{d ^{2} ψ _{c} ( y )}{d y ^{2}} - \frac{ψ _{c} ( y ) - ψ _{g a t e}}{λ ^{2}} = 0$

Jo parameter $λ$ emerge hota hai woh hai natural length:

$λ = \frac{ε _{s i}}{α ε _{o x}} t_{s i} t_{o x}$

jahan:

$ε_{s i}, ε_{o x}$ = silicon aur oxide ki permittivities,
$t_{s i}$ = silicon body thickness (fin ke liye, fin width $W_{f in}$ ... lekin sirf woh part jo gated hai),
$t_{o x}$ = gate-oxide thickness,
$α$ = gates ki sankhya: $α = 1$ (single/planar), $2$ (double-gate), $\approx 3$ (triple-gate/FinFET).

Design rule of thumb: SCE ko tolerable rakhne ke liye roughly chahiye: $L_{g} ≳ 5 - 6 λ .$ Toh $λ$ ko aadha karne se $L_{g}$ bhi aadha ho sakta hai ⇒ chhote, dense chips.

HOW does current scale? (Effective width)

Effective width $W_{e f f}$ per fin derive karna (WHY: current har conducting surface ke along flow karta hai, isliye widths add hote hain):

$W_{e f f} = do sidewalls 2 H_{f in} + top W_{f in}$

Ek tall, thin fin ke liye, $H_{f in} ≫ W_{f in}$ , isliye $W_{e f f} \approx 2 H_{f in}$ .

Worked Examples

Common Mistakes

Flashcards

What geometric change defines a FinFET vs a planar MOSFET?

Channel ek thin vertical silicon fin hai aur gate use teen sides (top + do sidewalls) se wrap karta hai, instead of ek flat gate jo planar channel ke upar hai.

Why were FinFETs introduced as

L_{g}

shrank?

Short-channel effects / DIBL / leakage suppress karne ke liye: multi-sided gate zyada strong electrostatic control deta hai isliye transistor chhote gate lengths par poori tarah OFF ho sakta hai.

Write the natural length formula and state what small

λ

means.

λ = ε_{s i} t_{s i} t_{o x} / (α ε_{o x})

; chhota

λ

= short-channel effects se better immunity (gate chhote

L_{g}

par bhi control banaye rakhta hai).

Three ways a FinFET reduces

λ

vs planar?

Thin fin (chhota

t_{s i}

), thin oxide (chhota

t_{o x}

), zyada gates (

α \approx 3

vs 1).

Effective width of one fin?

W_{e f f} = 2 H_{f in} + W_{f in} \approx 2 H_{f in}

tall thin fins ke liye.

Why is FinFET width "quantized"?

Current poore fins ki surfaces par flow karta hai; aap current ek fin ke units mein add karte ho, isliye total width =

N (2 H_{f in} + W_{f in})

Should fins be wide or narrow, and why?

Narrow — ek thin fin

λ

mein

t_{s i}

ko kam karta hai, gate control improve karta hai aur leakage reduce karta hai.

Roughly how does

L_{g}

relate to

λ

for good behavior?

L_{g} ≳ 5 - 6 λ

What does

α

represent in the

λ

formula?

Channel ko control karne wali gate surfaces ki sankhya (1 planar, 2 double-gate, ~3 FinFET, 4 GAA).

What is the successor to FinFET that increases

α

further?

Gate-All-Around (GAA) / nanosheet transistors,

α \to 4

(gate channel ko sab sides se gherta hai).

Recall Feynman: explain to a 12-year-old

Ek garden hose (channel) imagine karo jisme se paani tab flow karta hai jab tum jaane do. Tap (gate) use on aur off karta hai. Purane transistors mein tap sirf hose ke upar press karta tha — jab hoses chhote hue, tap use poori tarah squeeze nahi kar pata tha aur paani leak hone lagta tha. FinFET hose ko ek thin deewar ki tarah khada karta hai aur use teen sides se ek saath squeeze karta hai, taaki yeh poori tarah band ho jaye. Use khada karna bhi zyada paani flow karne deta hai — aapko wahi mazboot hose milti hai kam floor space mein. Thin aur tall = winning shape.

Connections

Planar MOSFET — woh predecessor jise FinFET improve karta hai.
Short-Channel Effects aur DIBL — woh problems jo FinFETs solve karti hain.
Gate-All-Around Transistor (GAA / nanosheet) — agla step, $α \to 4$ .
Poisson's Equation in MOS Electrostatics — natural length $λ$ ka origin.
Moore's Law aur Dennard Scaling — kyun hum $L_{g}$ shrink karte rahe.
Gate Oxide and High-k Dielectrics — $λ$ mein $t_{o x}$ term.