Exercises — FinFET transistor structure

The gate wraps the fin on the top plus the two vertical sidewalls → three gated surfaces → $\alpha \approx 3$. Look at the fin in figure s01: the orange gate hugs three faces of the blue fin.

That symbol is $\alpha$. It sits in the denominator of $\lambda =\sqrt{{\epsilon }_{si}{t}_{si}{t}_{ox}/(\alpha {\epsilon }_{ox})}$. A larger denominator makes the fraction smaller, so larger $\alpha \Rightarrow$ smaller $\lambda$ (better gate control). Wrapping more sides helps.

Small $\lambda$ means the gate keeps electrostatic control over the channel down to a shorter gate length, so we can shrink $L_g$ (via $L_g\gtrsim 5\lambda$) without the drain taking over — i.e. fewer Short-Channel Effects and less DIBL.

Step — cancel ${\epsilon }_0$ (WHY: it's in both permittivities, so it divides out and only the relative numbers 11.7 and 3.9 survive): $\frac{{\epsilon }_{si}}{{\epsilon }_{ox}}=\frac{11.7}{3.9}=3.$ Step — plug in: $\lambda =\sqrt{\frac{3}{2}\cdot 10\cdot 1}\text{nm}=\sqrt{15}\approx 3.87\text{nm}.$ Sanity: it sits between planar ($\sqrt{30}\approx 5.5$ nm, $\alpha =1$) and FinFET ($\sqrt{10}\approx 3.2$ nm, $\alpha =3$) — more gates, smaller $\lambda$. ✓

$L_g\gtrsim 5\lambda =5\times 3.87\approx 19.4\text{nm}.$

One fin (WHY: current runs along both sidewalls of height $H_{fin}$ and across the top of width $W_{fin}$, and conducting widths add): $W_{eff}=2H_{fin}+W_{fin}=2(50)+6=106\text{nm}.$ Three fins in parallel add up: $W_{eff,total}=3\times 106=318\text{nm}.$

Only $\alpha$ changes, from $1$ to $3$, and it sits under a square root: $\frac{{\lambda }_{fin}}{{\lambda }_{planar}}=\sqrt{\frac{1/3}{1/1}}=\frac{1}{\sqrt{3}}\approx \mathrm{0.577.}$ So $\lambda$ shrinks by $\sqrt{3}\approx 1.73\times$. Via $L_g\gtrsim 5\lambda$, the minimum gate length also shrinks by $1.73\times$: planar $\to 27.4$ nm, FinFET $\to 15.8$ nm. That $1.73\times$ headroom is the entire reason FinFETs replaced planar devices at advanced nodes.

$\lambda \propto \sqrt{t_{si}{t}_{ox}}$. To halve $\lambda$ you must make the product $t_{si}{t}_{ox}$ one quarter of its value (because $\sqrt{1/4}=1/2$).

• Knob A: cut $t_{si}$ to $1/4$ (a much thinner fin) — a $4\times$ reduction. Hard to etch that thin.
• Knob B: cut $t_{ox}$ to $1/4$ — a $4\times$ reduction. Limited by gate leakage / Gate Oxide and High-k Dielectrics.
• (Balanced option: cut each by $2\times$; then the product drops $4\times$ and $\lambda$ halves, spreading the burden.)

$W_{eff}=2(60)+8=128\text{nm},\frac{W_{fin}}{W_{eff}}=\frac{8}{128}=0.0625=6.25\%.$ The top contributes only $\approx 6\%$; the two sidewalls dominate. That's why $W_{eff}\approx 2H_{fin}$ is a fair shortcut for tall, thin fins — the top term is a small correction.

Step — one fin: $W_{eff}=2(45)+7=97\text{nm}.$ Step — how many needed (WHY $\lceil \rceil$: you can only add whole fins — width is quantized): $N=\lceil \frac{500}{97}\rceil =\lceil 5.15\rceil =6.$ Step — realised width: $W_{eff,total}=6\times 97=582\text{nm}(\ge 500✓).$ You overshoot to 582 nm because a partial fin is impossible.

First check both give $W_{eff}=120$: P $=2(56)+8=120$ ✓, Q $=2(40)+40=120$ ✓. Design P ($t_{si}=8$ nm): ${\lambda }_P=\sqrt{\frac{3}{3}\cdot 8\cdot 1}=\sqrt{8}\approx 2.83\text{nm}.$ Design Q ($t_{si}=40$ nm): ${\lambda }_Q=\sqrt{\frac{3}{3}\cdot 40\cdot 1}=\sqrt{40}\approx 6.32\text{nm}.$ Same current, but Q's fat fin gives $\lambda$ over twice as large → far worse short-channel control. Design P (tall, thin) wins. This is the "thin fins, tall fins" rule made numerical.

The constant part: $\frac{{\epsilon }_{si}}{{\epsilon }_{ox}}{t}_{si}{t}_{ox}=3\times 6\times 0.9=16.2{\text{nm}}^2$. (a) FinFET: ${\lambda }_3=\sqrt{16.2/3}=\sqrt{5.4}\approx 2.32$ nm. GAA: ${\lambda }_4=\sqrt{16.2/4}=\sqrt{4.05}\approx 2.01$ nm. (b) $L_g\gtrsim 5\lambda$: FinFET $\to 11.6$ nm, GAA $\to 10.1$ nm. (c) $\lambda \propto 1/\sqrt{\alpha }$, so the ratio $\sqrt{3/4}\approx 0.87$ (a 13% cut) is much milder than $\sqrt{1/3}\approx 0.58$ (a 42% cut). Because of the square root and diminishing returns, each extra gate helps less than the one before.

Step 1 — pin down $\lambda$ first (WHY: $\lambda$ depends only on $W_{fin}$ here, so it sets the fin thinness before we worry about count): $\lambda =\sqrt{\frac{3}{3}\cdot W_{fin}\cdot 1}=\sqrt{W_{fin}}.$ Need $\lambda \le 3\Rightarrow \sqrt{W_{fin}}\le 3\Rightarrow W_{fin}\le 9$ nm. Choose the thinnest allowed, $W_{fin}=5$ nm → $\lambda =\sqrt{5}\approx 2.24$ nm ✓ (comfortably under 3). Step 2 — max out height for most current per fin: $H_{fin}=60$ nm. $W_{eff}=2(60)+5=125\text{nm per fin}.$ Step 3 — count fins (ceiling, whole fins only): $N=\lceil \frac{400}{125}\rceil =\lceil 3.2\rceil =4,W_{eff,total}=4\times 125=500\text{nm}(\ge 400✓).$ Result: $W_{fin}=5$ nm, $H_{fin}=60$ nm, $N=4$ fins → $\lambda \approx 2.24$ nm, $W_{eff}=500$ nm. Both targets met.

Within a row of identical fins you'd normally keep $H_{fin}$ uniform for manufacturability, and even if you shrank all four, $W_{eff}$ jumps in steps of $2\Delta H$ per fin — it's continuous in $H_{fin}$ but you'd need $H_{fin}=(400-4\cdot 5/...)$-style tweaks that fight the etch process. The clean, standard lever is $N$ (whole fins), which makes width quantized: you land on the nearest multiple at or above target and accept the overshoot. Fine analog trimming is done with other devices, not by carving fractional fins.

The three formulas covered everything ::: $\lambda =\sqrt{{\epsilon }_{si}{t}_{si}{t}_{ox}/(\alpha {\epsilon }_{ox})}$ for control, $W_{eff}=2H_{fin}+W_{fin}$ for current, and $L_g\gtrsim 5\lambda$ tying them to gate length. The single biggest habit these exercises drill ::: undo the square root before reasoning about factors — $\lambda$ and $W_{eff}$ respond very differently to the same knob.