FinFET transistor structure: Worked examples — Hardware deep dive

This page is a drill. The parent note built the two master formulas; here we push them into every corner case so no exam or real chip surprises you.

Before touching numbers, we must re-earn every symbol, because a formula you can't read is useless.

Definition

The symbols in the two master formulas (all lengths in nanometres, nm):

$ε_{s i}$ = permittivity ("electric stiffness") of the silicon body; $ε_{o x}$ = permittivity of the gate oxide. $ε_{0}$ is a fixed constant of nature; we only ever use the ratio $ε_{s i} / ε_{o x}$ , in which $ε_{0}$ cancels.
$t_{s i}$ = thickness of the silicon body (the fin width); $t_{o x}$ = thickness of the gate oxide.
$α$ = the number of gated surfaces controlling the channel. Picture the channel as a wall and $α$ counts from how many sides a gate grips it: $α = 1$ (planar, top only), $2$ (double-gate), $3$ (FinFET: top + two sidewalls), $4$ (GAA, all around). It is a count of gates, not a thickness.
$L_{g}$ = gate length (how long the gate runs along the channel).
$H_{f in}$ = fin height (how tall the silicon wall stands); $W_{f in}$ = fin width (how thick that wall is — the same quantity as $t_{s i}$ ).
$N$ = the number of parallel fins you place side by side (a whole number: 1, 2, 3, …).

With every symbol now defined and pictured, here are the two tools:

Because the relative permittivities are fixed, $ε_{s i} / ε_{o x} = 11.7/3.9 = 3$ throughout. We use that shortcut constantly.

The two figures below are the pictures behind $λ$ and $W_{e f f}$ — read them first, then the algebra becomes obvious.

Figure 1 — what $λ$ means geometrically: it is the depth to which the drain's field leaks into the channel; more gates squeeze that leak shorter.

Figure 2 — what $W_{e f f}$ is: the perimeter of channel a fin's cross-section exposes (two pink sidewalls + one yellow top).

The scenario matrix

Every problem this topic can throw is one of these cells. Each worked example below is tagged with the cell(s) it covers.

Cell	What it tests	Where it bites
A. Gate count $α$	$α = 1$ vs $2$ vs $3$ vs $4$	planar → double-gate → FinFET → GAA
B. High- $k$ swap	change $ε_{o x}$ (oxide material)	high-k dielectrics shrink $λ$
C. Degenerate geometry	$t_{s i} \to 0$ , $t_{o x} \to 0$ , one factor huge	limiting behaviour of $λ$
D. Design-rule inversion	given target $L_{g}$ , solve for allowed $t_{s i}$	rearranging the $λ$ formula
E. $W_{e f f}$ quantization	need $N$ whole fins, ceil rounding	you always overshoot
F. Tall-thin limit	$H_{f in} ≫ W_{f in}$ vs square fin	when $W_{e f f} \approx 2 H_{f in}$ holds/fails
G. Word problem	real chip: match a planar width budget	layout translation
H. Exam twist	trap combining two effects at once	thicker fin and more gates fight

Cell A + B — Gate count and oxide material

Collapse the permittivity ratio. $\frac{ε _{s i}}{ε _{o x}} = \frac{11.7 ε _{0}}{3.9 ε _{0}} = 3.$ Why this step? Only the ratio enters $λ$ , and $ε_{0}$ cancels, so we never need its numeric value.
Reduce to one clean expression. $λ = \frac{3 \cdot 10 \cdot 1}{α} nm = \frac{30}{α} nm .$ Why this step? Everything except $α$ is now a fixed number ( $30$ ), so we see the $α$ -dependence at a glance.
Evaluate each gate count. $α = 1 : 30 \approx 5.48 nm α = 2 : 15 \approx 3.87 nm$ $α = 3 : 10 \approx 3.16 nm α = 4 : 7.5 \approx 2.74 nm$ Why this step? $α = 1$ is planar, $α = 3$ is the FinFET, $α = 4$ is GAA/nanosheet.

Verify: $λ \propto 1/ α$ , so going $α = 1 \to 4$ should cut $λ$ by $4 = 2$ : $5.48/2.74 \approx 2.0$ ✓. Doubling gates only divides $λ$ by $2 \approx 1.41$ , not by 2 — the forecast trap.

New ratio. $ε_{s i} / ε_{o x} = 11.7/25 = 0.468$ . Why this step? A bigger oxide permittivity shrinks the ratio.
Plug in. $λ = \frac{0.468 \cdot 10 \cdot 1}{3} = 1.56 \approx 1.25 nm .$ Why this step? Same structure, only the ratio changed.

Verify: $λ$ dropped from $3.16$ nm to $1.25$ nm — smaller, hence better electrostatics. This is why real FinFETs use high- $k$ dielectrics: a bigger $ε_{o x}$ in the denominator shrinks $λ$ . ✓

Cell C — Degenerate & limiting geometry

$t_{s i} \to 0$ (ultra-thin body). $λ = \frac{3 \cdot 0 \cdot t _{o x}}{3} = 0.$ Why this step? A zero product under the root gives zero. Physically $λ \to 0$ means perfect gate control — the drain field cannot penetrate. This is the ideal limit FinFETs chase (thin fins!).
$t_{o x} \to 0$ (perfect oxide). Same algebra: $λ \to 0$ . Why? Thinner oxide = gate closer to channel = tighter grip.
Both large (bad case), $t_{s i} = t_{o x} = 100$ nm. $λ = \frac{3 \cdot 100 \cdot 100}{3} = 10000 = 100 nm .$ Why this step? Fat body + fat oxide = huge $λ$ = the gate loses control long before the drain — full-blown Short-Channel Effects.

Verify: each limit is monotone: $λ$ increases with $t_{s i}$ and $t_{o x}$ , decreases with $α$ . The zero cases are consistent (product hits 0 ⇒ root is 0). ✓

Cell D — Design-rule inversion

Turn the rule into a $λ$ ceiling. $λ \leq \frac{L _{g}}{5} = \frac{15}{5} = 3 nm .$ Why this step? The design rule is a bound on $λ$ , so first find that bound.
Square the natural-length formula to free $t_{s i}$ . $λ^{2} = \frac{3 t _{s i} ( 1 )}{3} = t_{s i} .$ Why this step? Squaring undoes the square root so $t_{s i}$ comes out linearly — the algebra collapses neatly because the constants happen to cancel to 1.
Apply the ceiling. $t_{s i} = λ^{2} \leq 3^{2} = 9 nm .$ Why this step? $t_{s i}$ is directly $λ^{2}$ here, so the max fin width is $9$ nm.

Verify: plug $t_{s i} = 9$ back: $λ = 3 \cdot 9 \cdot 1/3 = 9 = 3$ nm, and $5 λ = 15 = L_{g}$ ✓. Any fatter fin breaks the rule.

Cells E + F — Effective width, quantization, tall-thin limit

Read Figure 3 first: it plots $W_{e f f} = N \times W_{e f f, 1}$ as a staircase, so you literally see why the answer must jump to a whole fin.

One-fin width. $W_{e f f, 1} = 2 (42) + 6 = 84 + 6 = 90 nm .$ Why this step? Two sidewalls carry current ( $2 H_{f in}$ ) plus the top ( $W_{f in}$ ).
Raw fin count. $\frac{250}{90} = 2.78.$ Why this step? This is how many fins the target wants — but fins are whole objects.
Ceil to whole fins. $N = ⌈ 2.78 ⌉ = 3.$ Why this step? You cannot etch a fractional fin; width is quantized. Round up so you meet (or exceed) the target — trace the red target line up to the first step that clears it in Figure 3.
Actual width. $W_{e f f} = 3 \times 90 = 270 nm .$

Verify: $270 \geq 250$ ✓ (target met), and $2 \times 90 = 180 < 250$ ✓ (two fins would fail). The overshoot of $20$ nm is the price of quantization. ✓

Look again at Figure 2: the top slice (yellow) is what the shortcut throws away. When the wall is tall, that slice is a rounding error; when it is square, it is a big chunk.

Tall-thin exact. $W_{e f f} = 2 (50) + 5 = 105$ nm; shortcut $2 H_{f in} = 100$ nm. Why this step? Compare exact vs shortcut to size the error.
Tall-thin error. $(105 - 100) /105 = 4.8%$ — small. Why? The top ( $W_{f in}$ ) is a tiny slice of the perimeter.
Square exact. $W_{e f f} = 2 (10) + 8 = 28$ nm; shortcut $2 H_{f in} = 20$ nm. Why this step? Now the top is a big fraction.
Square error. $(28 - 20) /28 = 28.6%$ — large. Why? When $W_{f in}$ is comparable to $H_{f in}$ , ignoring the top is a real mistake.

Verify: shortcut is good ( $< 5%$ ) only when $H_{f in} ≫ W_{f in}$ ✓. Square fins need the full formula. This is exactly why real fins are drawn tall and thin.

Cell G — Real-world word problem

Per-fin width. $W_{e f f, 1} = 2 (45) + 8 = 98$ nm. Why this step? Every fin contributes the same perimeter of channel.
Fins needed. $520/98 = 5.31 \Rightarrow N = ⌈ 5.31 ⌉ = 6$ . Why this step? Match the old budget, round up to whole fins.
Delivered width. $W_{e f f} = 6 \times 98 = 588$ nm. Why this step? Report what the layout truly provides.

Verify: $588 \geq 520$ ✓; five fins give $490 < 520$ ✓ (insufficient). The FinFET version delivers the planar drive strength with margin, packed in a smaller footprint — the scaling win. ✓

Cell H — Exam twist (two effects fighting)

Baseline planar. $λ_{1} = 3 \cdot 10 \cdot 1/1 = 30 \approx 5.48$ nm. Why this step? Establish the "before."
New FinFET with fat fin. $λ_{2} = 3 \cdot 20 \cdot 1/3 = 20 \approx 4.47$ nm. Why this step? Both changes applied at once — that's the trap.
Compare. $4.47 < 5.48$ : $λ$ did improve, but only by $1.23 \times$ . Why this step? The $\times 3$ gates ( $\div 3 = 1.73$ ) barely beat the $\times 2$ thickness ( $\times 2 = 1.41$ ); net factor $= 3/ (2 \cdot 1) = 1.5 \approx 1.22$ .
The right move. Keep the thin fin ( $t_{s i} = 10$ ) and $α = 3$ : $λ = 10 \approx 3.16$ nm — far better. Why this step? Never trade away thin-fin electrostatics for width; get width from height ( $W_{e f f} \approx 2 H_{f in}$ ) instead.

Verify: $20 \approx 4.47$ and $30 / 20 = 1.5 \approx 1.22$ ✓; the thin-fin FinFET $10 \approx 3.16$ beats both ✓. The exam lesson: thin fins for control, tall fins for current — the leakage-vs-drive trade must be won on the right axis.

Recall

Why does doubling $α$ divide $λ$ by only $2$ , not 2? ::: $α$ sits under a square root: $λ \propto 1/ α$ , so $\times 2$ gates $\Rightarrow \div 2 \approx 1.41$ . In Example 5, why $N = 3$ and not $2.78$ ? ::: Fins are whole; width is quantized, so you ceil up to meet the target and overshoot to $270$ nm. When is $W_{e f f} \approx 2 H_{f in}$ safe to use? ::: Only in the tall-thin limit $H_{f in} ≫ W_{f in}$ (error under ~5%); square fins need the full $2 H_{f in} + W_{f in}$ . High- $k$ oxide raises $ε_{o x}$ — why does that help? ::: $ε_{o x}$ is in the denominator of $λ$ ; bigger $ε_{o x}$ shrinks $λ$ , tightening gate control.

Worked examples — FinFET transistor structure